7.1.1. Cortex-M23 processor ROM table identification and entries

Table 7.1 shows the CoreSight components that the Cortex-M23 processor ROM table points to. The values depend on the implemented debug configuration.

Table 7.1. Cortex-M23 processor ROM table components

AddressComponentValueDescription
0xE00FF000SCS0xFFF0F003See System Control Space.
0xE00FF004DWT0xFFF02003[a]See Data watchpoint unit.
0xE00FF008FPB0xFFF03003[b]See Flash Patch and Breakpoint unit.
0xE00FF00CReserved0xFFF01002-
0xE00FF010Reserved0xFFF41002-
0xE00FF014ETM0xFFF42003[c]See Embedded Trace Macrocell.
0xE00FF018CTI0xFFF43003[d]See Cross Trigger Interface.
0xE00FF01CMTB0xFFF44003[e]See Micro Trace Buffer.
0xE00FF020End marker0x00000000See the ARM®v8-M Architecture Reference Manual.

[a] Reads as 0xFFF02002 if no watchpoints are implemented.

[b] Reads as 0xFFF03002 if no breakpoints are implemented.

[c] Reads as 0xFFF42002 if ETM is not implemented.

[d] Reads as 0xFFF43002 if CTI is not implemented.

[e] Reads as 0xFFF44002 if MTB is not implemented.


The SCS, DWT, FPB, ETM, MTB, and CTI ROM table entries point to the debug components at addresses 0xE000E000, 0xE0001000, 0xE0002000, 0xE0041000, 0xE0043000, and 0xE0042000 respectively. The value for each entry is the offset of that component from the ROM table base address, 0xE00FF000.

Table 7.2 shows the ROM table identification registers and values for debugger detection. This enables debuggers to identify the processor and its debug capabilities.

Note

The Cortex-M23 processor ROM table only supports word size transactions.

Table 7.2. Cortex-M23 processor ROM table identification values

AddressRegisterValueDescription
0xE00FFFD0Peripheral ID40x00000004Component and peripheral ID register formats in the ARM®v8-M Architecture Reference Manual.
0xE00FFFE0Peripheral ID00x000000CB
0xE00FFFE4Peripheral ID10x000000B4
0xE00FFFE8Peripheral ID20x0000000B
0xE00FFFECPeripheral ID30x00000000
0xE00FFFF0Component ID00x0000000D
0xE00FFFF4Component ID10x00000010
0xE00FFFF8Component ID20x00000005
0xE00FFFFCComponent ID30x000000B1

See the ARM®v8-M Architecture Reference Manual and the CoreSight SoC-400 Technical Reference Manual for more information about the ROM table ID and component registers, and their addresses and access types.

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