7.1.3. Data watchpoint unit

The Cortex-M23 processor DWT implementation provides between zero and four watchpoint register sets. A processor that is configured with zero watchpoint implements no watchpoint functionality and the ROM table shows that no DWT is implemented.

DWT functionality

The processor watchpoints implement both data address and PC based watchpoint functionality, a PC sampling register, and support comparator address masking, as described in the ARM®v8-M Architecture Reference Manual.

DWT CoreSight identification

Table 7.4 shows the DWT identification registers and values for debugger detection.

Table 7.4. DWT identification values

0xE0001FD0Peripheral ID40x00000004See the ARM®v8-M Architecture Reference Manual.
0xE0001FE0Peripheral ID00x00000020
0xE0001FE4Peripheral ID10x000000BD
0xE0001FE8Peripheral ID20x0000000B
0xE0001FECPeripheral ID30x00000000
0xE0001FF0Component ID00x0000000D
0xE0001FF4Component ID10x00000090
0xE0001FF8Component ID20x00000005
0xE0001FFCComponent ID30x000000B1

See the ARM®v8-M Architecture Reference Manual and the ARM® CoreSight™ SoC-400 Technical Reference Manual for more information about the DWT CoreSight identification registers, and their addresses and access types.

DWT Program Counter Sample Register

The Cortex-M23 processor implements the ARMv8-M optional DWT Program Counter Sample Register (DWT_PCSR) when there is at least one DWT. This register enables a debugger to periodically sample the PC without halting the processor. This provides coarse grained profiling. See the ARM®v8-M Architecture Reference Manual for more information.

The Cortex-M23 processor DWT_PCSR records both instructions that pass their condition codes and those instructions that fail.

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