6.3. MPU register summary

Table 6.3 shows the MPU registers. Each of these registers is 32 bits wide. If the MPU is not present in the implementation, then all these registers read as zero.

Table 6.3. MPU registers

NameReset valueDescription
MPU_TYPE[a]0x0000XX00MPU Type Register.
MPU_CTRL0x00000000MPU Control Register.
MPU_RNRUNKNOWNMPU Region Number Register.
MPU_RBARUNKNOWNMPU Region Base Address Register.
MPU_RLARUNKNOWNMPU Region Limit Address Register
MPU_MAIR0UNKNOWNMPU Memory Attribute Indirection Register 0
MPU_MAIR1UNKNOWNMPU Memory Attribute Indirection Register 1

[a] Bits[15:8] depend on the number of MPU regions included. This value can be 0, 4, 8, 12, or 16.


  • See the ARM®v8-M Architecture Reference Manual for more information about the MPU registers and their addresses, access types, and reset values.

  • If the Security Extension is implemented, the registers are aliased.

  • The MPU supports region sizes from 32 bytes to 4GB.

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