2.2.1. AMBA 5 AHB interface

Transactions on the AMBA 5 AHB interface are always marked as non-sequential.

Processor accesses and debug accesses share the same external interface to external AHB peripherals. The processor accesses take priority over debug accesses.

Any vendor-specific components can populate this bus.


Instructions are only fetched using the AMBA 5 AHB interface. To optimize performance, the processor fetches ahead of the instruction it is executing. To minimize power consumption, the fetch ahead is limited to a maximum of 32-bits.

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