3.3. Instruction set summary

The processor implements the entire ARMv8-M baseline instruction set.

Table 3.1 shows the Cortex-M23processor instructions and their cycle counts. The cycle counts are based on a system with zero wait-states on the AHB bus.

Table 3.1. Cortex-M23 processor instruction summary

Operation DescriptionAssembler Cycles
Move8-bit immediateMOVS <Rd>, #<imm>1
Lo to Lo[a]MOVS <Rd>, <Rm>1
Any to Any[b]MOV <Rd>, <Rm>1
Any[b] to PCMOV PC, <Rm>2
TopMOVT <Rd>, #<imm>3
WideMOVW <Rd>, #<imm>3
Add3-bit immediateADDS <Rd>, <Rn>, #<imm>1
All registers Lo[a]ADDS <Rd>, <Rn>, <Rm>1
Any to Any[b]ADD <Rd>, <Rd>, <Rm>1
Any[b] to PCADD PC, PC, <Rm>2
8-bit immediateADDS <Rd>, <Rd>, #<imm>1
With carryADCS <Rd>, <Rd>, <Rm>1
Immediate to SPADD SP, SP, #<imm>1
Form address from SPADD <Rd>, SP, #<imm>1
Form address from PCADR <Rd>, <label>1
SubtractLo and Lo[a]SUBS <Rd>, <Rn>, <Rm>1
3-bit immediateSUBS <Rd>, <Rn>, #<imm>1
8-bit immediateSUBS <Rd>, <Rd>, #<imm>1
With carrySBCS <Rd>, <Rd>, <Rm>1
Immediate from SPSUB SP, SP, #<imm>1
NegateRSBS <Rd>, <Rn>, #01
MultiplyMultiplyMULS <Rd>, <Rm>, <Rd>1 or 32[c]
DivideUnsignedUDIV {<Rd>,} <Rn>, <Rm>17 or 34[d]
SignedSDIV {<Rd>,} <Rn>, <Rm>17 or 34[d]
CompareCompareCMP <Rn>, <Rm>1
NegativeCMN <Rn>, <Rm>1
ImmediateCMP <Rn>, #<imm>1
Compare and Branch on Non-ZeroCBNZ <Rn>, <label>2 or 1[e]
Compare and Branch on ZeroCBZ <Rn>, <label>2 or 1[e]
LogicalANDANDS <Rd>, <Rd>, <Rm>1
Exclusive OREORS <Rd>, <Rd>, <Rm>1
ORORRS <Rd>, <Rd>, <Rm>1
Bit clearBICS <Rd>, <Rd>, <Rm>1
Move NOTMVNS <Rd>, <Rm>1
AND testTST <Rn>, <Rm>1
Shift Logical shift left by immediateLSLS <Rd>, <Rm>, #<shift>1
Logical shift left by registerLSLS <Rd>, <Rd>, Rs1
Logical shift right by immediateLSRS <Rd>, <Rm>, #<shift>1
Logical shift right by registerLSRS <Rd>, <Rd>, Rs1
Arithmetic shift rightASRS <Rd>, <Rm>, #<shift>1
Arithmetic shift right by registerASRS <Rd>, <Rd>, Rs1
RotateRotate right by registerRORS <Rd>, <Rd>, Rs1
ClearExclusiveCLREX1
LoadWord, immediate offsetLDR <Rd>, [<Rn>, #<imm>]2 or 1[f]
Halfword, immediate offset

LDRH <Rd>, [<Rn>, #<imm>]

2 or 1[f]
Byte, immediate offset

LDRB <Rd>, [<Rn>, #<imm>]

2 or 1[f]
Word, register offsetLDR <Rd>, [<Rn>, <Rm>]2 or 1[f]
Halfword, register offsetLDRH <Rd>, [<Rn>, <Rm>]2 or 1[f]
Signed halfword, register offsetLDRSH <Rd>, [<Rn>, <Rm>]2 or 1[f]
Byte, register offsetLDRB <Rd>, [<Rn>, <Rm>]2 or 1[f]
Signed byte, register offsetLDRSB <Rd>, [<Rn>, <Rm>]2 or 1[f]
PC-relativeLDR <Rd>, <label>2 or 1[f]
SP-relativeLDR <Rd>, [SP, #<imm>]2 or 1[f]
Multiple, excluding baseLDM <Rn>!, {<loreglist>}[g]1+N[h]
Multiple, including baseLDM <Rn>, {<loreglist>}[g]3+N[h]
Exclusive WordLDREX Rt, [<Rn>{,#<imm>}]4
Exclusive HalfwordLDREXH Rt, [<Rn>]4
Exclusive ByteLDREXB Rt, [<Rn>]4
Acquire WordLDA Rt, [<Rn>]3 or 2[i]
Acquire HalfwordLDAH Rt, [<Rn>]3 or 2[i]
Acquire ByteLDAB Rt, [<Rn>]3 or 2[i]
Acquire Exclusive WordLDAEX Rt, [<Rn>]4
Acquire Exclusive HalfwordLDAEXH Rt, [<Rn>]4
Acquire Exclusive ByteLDAEXB Rt, [<Rn>]4
StoreWord, immediate offsetSTR <Rd>, [<Rn>, #<imm>]2 or 1[f]
Halfword, immediate offsetSTRH <Rd>, [<Rn>, #<imm>]2 or 1[f]
Byte, immediate offsetSTRB <Rd>, [<Rn>, #<imm>]2 or 1[f]
Word, register offsetSTR <Rd>, [<Rn>, <Rm>]2 or 1[f]
Halfword, register offsetSTRH <Rd>, [<Rn>, <Rm>]2 or 1[f]
Byte, register offsetSTRB <Rd>, [<Rn>, <Rm>]2 or 1[f]
SP-relativeSTR <Rd>, [SP, #<imm>]2 or 1[f]
MultipleSTM <Rn>!, {<loreglist>}[g]1+N[h]
Exclusive WordSTREX <Rd>, Rt, [<Rn> {,#<imm>}]4
Exclusive HalfwordSTREXH <Rd>, Rt, [<Rn>]4
Exclusive ByteSTREXB <Rd>, Rt, [<Rn>]4
Acquire WordSTL Rt, [<Rn>]3 or 2[i]
Acquire HalfwordSTLH Rt, [<Rn>]3 or 2[i]
Acquire ByteSTLB Rt, [<Rn>]3 or 2[i]
Acquire Exclusive WordSTLEX <Rd>, Rt, [<Rn>]4
Acquire Exclusive HalfwordSTLEXH <Rd>, Rt, [<Rn>]4
Acquire Exclusive ByteSTLEXB <Rd>, Rt, [<Rn>]4
PushPushPUSH {<loreglist>}[g]1+N[h]
Push with link registerPUSH {<loreglist>, LR}[g]1+N[j]
PopPopPOP {<loreglist>}[g]1+N[h]
Pop and returnPOP {<loreglist>, PC}[g]3+N[j]
Pop and function returnPOP {<loreglist>, PC}[g]3+N[j]
BranchConditionalB<c> <label>1 or 2[k]
UnconditionalB <label>2
To targetB.W <label>3
With linkBL <label>3
And exchangeBX <Rm>2
And exchange Non-secureBXNS <Rm>4
With function return and exchangeBX{NS} <Rm>4
With link and exchangeBLX <Rm>2
With link and exchange Non-secureBLXNS <Rm>4
ExtendSigned halfword to wordSXTH <Rd>, <Rm>1
Signed byte to wordSXTB <Rd>, <Rm>1
Unsigned halfwordUXTH <Rd>, <Rm>1
Unsigned byteUXTB <Rd>, <Rm>1
ReverseBytes in wordREV <Rd>, <Rm>1
Bytes in both halfwordsREV16 <Rd>, <Rm>1
Signed bottom halfwordREVSH <Rd>, <Rm>1
State changeSupervisor CallSVC #<imm>- [l]
Disable interruptsCPSID i1
Enable interruptsCPSIE i1
Read special registerMRS <Rd>, <specreg>[m]3
Write special registerMSR <specreg>, <Rn>[m]3
BreakpointBKPT #<imm>- [l]
HintSend eventSEV1
Wait for eventWFE2[n]
Wait for interruptWFI2[n]
YieldYIELD1[o]
No operationNOP1
BarriersInstruction synchronizationISB3
Data memoryDMB3
Data synchronizationDSB3
GatewaySecure GatewaySG3
TestTest TargetTT{A}{T} <Rd>, <Rn>3

[a] Lo indicates registers R0-R7.

[b] Any indicates registers R0-R15.

[c] Depends on multiplier implementation.

[d] Depends on divider implementation.

[e] 2 if the branch is taken, 1 if the branch is not taken.

[f] 2 if to AHB interface or SCS, 1 if to single-cycle I/O port.

[g] loreglist indicates registers R0-R7.

[h] N is the number of elements in the list.

[i] 3 if to AHB interface or SCS, 2 if to single-cycle I/O port.

[j] N is the number of elements in the list including PC or LR.

[k] 2 if taken, 1 if not-taken.

[l] Cycle count depends on processor and debug configuration.

[m] specreg indicates special-purpose registers

[n] Excludes time that is spent waiting for an interrupt or event.

[o] Executes as NOP.


See the ARM®v8-M Architecture Reference Manual for more information about the instructions.

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