3.6.1. Exception handling

The processor implements advanced exception and interrupt handling, as described in the ARM®v8-M Architecture Reference Manual.

To minimize interrupt latency, the processor abandons any load-multiple or store-multiple instruction to take any pending interrupt. On return from the interrupt handler, the processor restarts the load-multiple or store-multiple instruction from the beginning.


  • A processor that implements the 32-cycle multiplier abandons multiply instructions in the same way.

  • The processor abandons both 17-cycle and 34-cycle divide instructions in the same way.

  • When a BX or POP PC causes a function return, the instruction becomes non-interruptible during unstacking phase.

This means that software must not use load-multiple or store-multiple instructions when a device is accessed in a memory region that is read-sensitive or sensitive to repeated writes. The software must not use these instructions in any case where repeated reads or writes might cause inconsistent results or unwanted side-effects.

The processor implementation can ensure that a fixed number of cycles are required for the NVIC to detect an interrupt signal and the processor fetch the first instruction of the associated interrupt handler. If this is done, the highest priority interrupt is jitter-free. See the documentation that is supplied by the processor implementer for more information.

To reduce interrupt latency and jitter, the Cortex-M23 processor implements both interrupt late-arrival and interrupt tail-chaining mechanisms, as defined by the ARMv8-M architecture.

In a zero wait-state system, excluding late arriving interrupts:


  • The number of cycles are cycles after the interrupt is set, up to the data phase of the first instruction in the handler.

  • If the Security Extension is implemented, this number assumes no fault happening during interrupt return and stacking. Latency cannot be guaranteed in case of fault.

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