3.5. Registers summary

Table 3.3 shows the processor register set summary. Each of these registers is 32 bits wide.

Table 3.3. Core register set summary

NameDescription
R0-R12R0-R12 are general-purpose registers for data operations.
MSP (R13)

The Stack Pointer (SP) is register R13. In Thread mode, the CONTROL registers indicate the Stack Pointers to use, Main Stack Pointer (MSP) or Process Stack Pointer (PSP).

If the Security Extension is implemented:

There are two MSP registers in the Cortex-M23 processor:

  • MSP_NS for the Non-secure state.

  • MSP_S for the Secure state.

There are two PSP registers in the Cortex-M23 processor.

  • PSP_NS for the Non-secure state.

  • PSP_S for the Secure state.

If the Security Extension is not implemented:

There is one MSP register and one PSP register in the Cortex-M23 processor.

PSP (R13)
MSPLIM_S[a]The stack limit registers limit the extent to which the MSP_S and PSP_S registers can descend respectively.
PSPLIM_S[a]
LR (R14)The Link Register (LR) is register R14. It stores the return information for subroutines, function calls, and exceptions.
PC (R15)The Program Counter (PC) is register R15. It contains the current program address.
PSR

The Program Status Register (PSR) combines:

  • Application Program Status Register (APSR).

  • Interrupt Program Status Register (IPSR).

  • Execution Program Status Register (EPSR).

These registers provide different views of the PSR.

PRIMASK

The PRIMASK register prevents activation of all exceptions with configurable priority. For information about the exception model the processor supports, see Exceptions.

If the Security Extension is implemented:

There are two PRIMASK registers in the Cortex-M23 processor:

  • PRIMASK_NS for the Non-secure state.

  • PRIMASK_S for the Secure state.

If the Security Extension is not implemented:

There is one PRIMASK register in the Cortex-M23 processor.

CONTROL

The CONTROL registers control the stack that is used, and optionally the code privilege level, when the processor is in Thread mode.

If the Security Extension is implemented:

There are two CONTROL registers in the Cortex-M23 processor:

  • CONTROL_NS for the Non-secure state.

  • CONTROL_S for the Secure state.

If the Security Extension is not implemented:

There is one CONTROL register in the Cortex-M23 processor.

[a] If Security Extension is not implemented, the Cortex-M23 processor does not support stack limit registers.


See the ARM®v8-M Architecture Reference Manual for information about the processor registers and their addresses, access types, and reset values.

Note

PUSH instructions starting below the stack limit are not performed. Exception stacking going below the limit may be partially written on the memory for address equal to or above the stack limit.

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