2.1. About the functions

The Cortex-M23 processor is a configurable, two-stage, 32-bit RISC processor. It has an AMBA 5 AHB interface and includes an NVIC component. It also has optional hardware debug, single-cycle I/O interfacing, and memory-protection functionality. The processor also supports the Security Extension.

Figure 2.1 shows the functional blocks of the processor.

Figure 2.1. Functional block diagram

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The implemented device provides:

A low gate count processor that features:
  • The ARMv8-M baseline Thumb-2 instruction set.

  • Optional Security Extension, including a Secure and a Non-secure state.

  • Optionally, an ARMv8-M-compliant 24-bit SysTick timer for each security domain.

  • A 32-bit hardware multiplier. This can be the standard single-cycle multiplier, or a 32-cycle multiplier that has a smaller area and lower performance implementation.

  • A 32-bit hardware divider. This can be the fast 17-cycle divider, or a slower 34-cycle divider.

  • Support for either little-endian (LE) or byte invariant big-endian (BE8) data accesses.

  • The ability to have deterministic and fixed-latency interrupt handling.

  • Load/store multiple, multicycle multiply and division instructions that can be abandoned to facilitate rapid interrupt handling.

  • Unprivileged/privileged support for improved system integrity.

  • C Application Binary Interface compliant exception model.

    This is the ARMv8-M, C Application Binary Interface (C-ABI) compliant exception model that enables the use of pure C functions as interrupt handlers.

  • Low-power sleep-mode entry using Wait For Interrupt (WFI), Wait For Event (WFE) instructions, or the return from interrupt sleep-on-exit feature.

NVIC that features:
  • Up to 240 external interrupt inputs, each with four levels of priority.

  • Dedicated Non-Maskable Interrupt (NMI) input.

  • Support for both level-sensitive and pulse-sensitive interrupt lines.

    Note

    There is no internal register to differentiate that the interrupt was pulse or level and no configuration option to support one or the other.

  • Optional Wake-up Interrupt Controller (WIC), providing ultra-low power sleep mode support.

Optional debug support:
  • Halting mode debug only.

  • Zero to four hardware breakpoints.

  • Zero to four watchpoints.

  • Program Counter Sample Register (PCSR) for non-intrusive code profiling, if at least one hardware data watchpoint is implemented.

  • Single step and vector catch capabilities.

  • Breakpoint comparators that allow instruction address matching.

  • Support for unlimited software breakpoints using the BKPT instruction.

  • Non-intrusive access to core peripherals and zero-wait state system slaves through a compact bus matrix. A debugger can access these devices, including memory, even when the processor is running.

  • Full access to core registers when the processor is halted.

  • Optional, low gate-count CoreSight™ compliant debug access through a Debug Access Port (DAP) supporting either Serial Wire or JTAG debug connections.

Bus interfaces:
  • Single 32-bit AMBA 5 AHB system interface that provides simple integration to all system peripherals and memory.

  • Optional single 32-bit single-cycle I/O port.

  • Optional single 32-bit slave port that supports the DAP.

Optional Non-secure Memory Protection Unit (MPU):
  • Up to 16 user configurable memory regions.

  • eXecute-Never (XN) support.

Optional Secure Memory Protection Unit (MPU):
  • Present only if the Security Extension is implemented.

  • Up to 16 user configurable memory regions.

  • eXecute-Never (XN) support.

Optional Security Attribution Unit (SAU):
  • Present only if the Security Extension is implemented.

  • Up to eight user configurable memory regions.

  • External Implementation Defined Attribution Unit (IDAU). This interface is always present, but is ignored if the Security Extension is not implemented.

Optional Embedded Trace Macrocell (ETM):
  • Provides a complete instruction trace solution.

  • Configurable by an APB slave.

  • For more information, see the ARM® CoreSight™ ETM-M23 Technical Reference Manual.

Optional Micro Trace Buffer (MTB):
  • Provides a simple execution trace capability for the processor.

  • It offers a lower-cost alternative that has certain limitations compared to ETM.

  • For more information, see the ARM® CoreSight™ MTB-M23 Technical Reference Manual.

Optional Cross Trigger Interface (CTI):
  • Enables the debug logic and the ETM to interact with each other and with other CoreSight components.

Optional Trace Port Interface Unit (TPIU):
  • Present by default when ETM is used.

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