1.6. Configurable options

Table 1.1 shows the processor configurable options available at implementation time.

Table 1.1. Processor configurable options

FeatureConfigurable option
Security Extension[a]Present or absent.
Non-secure MPU4, 8, 12, 16 regions, or absent.
Secure MPU[b]4, 8, 12, 16 regions, or absent.
SAU[b]Absent, 4-region, or 8-region.

SysTick timers

  • If the Security Extension is not implemented, can be present or absent.

  • If the Security Extension is implemented, 0, 1, or 2 SysTick timers can be present. If only one, it is configurable by software if it is Secure or not.

Vector Table Offset Register (VTOR)[c]
  • If the Security Extension is not implemented, can be present or absent.

  • If the Security Extension is implemented, can be either present or absent for both security states.

Reset all registersPresent or absent.
MultiplierFast (one cycle) or slow (32 cycles).
DividerFast (17 cycles) or slow (34 cycles).
Interrupts

External interrupts 1-240.

Instruction fetch width16-bit only or 32-bit.
Single-cycle I/O portPresent or absent.
Architectural clock gating presentWhen set, architectural clock gating cells are instantiated.
Data endianness[d]Little-endian or byte-invariant big-endian.

Halting debug support

Present or absent.

Wake-up interrupt controllerSupported or not supported.
Number of breakpoint comparators[e]0, 1, 2, 3, 4.
Number of watchpoint comparators[e]0, 1, 2, 3, 4.
Cross Trigger Interface (CTI)[e]Present or absent.
Micro Trace Buffer (MTB)[e]Present or absent.
Embedded Trace Macrocell (ETM)[e]Present or absent.
JTAGnSW debug protocolSelects between JTAG or Serial-Wire interfaces for the DAP.
Multi-drop support for Serial Wire[f]Present or absent.
Slave port support for AHB DAPWhen set, include slave port support for any AHB DAP implementation. Otherwise, support only the low area DAP.

[a] There is also the possibility to add or remove the Security Extension with a fuse (input pin).

[b] Requires the Security Extension to be present.

[c] If the Security Extension is implemented, there is no option to have only one VTOR register. The options are either zero or two.

If the Security Extension is not implemented, there is no option to have two VTOR registers. The options are either zero or one.

[d] Instruction fetches and PPB accesses are always little-endian.

[e] Only when Halting debug support is present.

[f] Requires Serial-Wire interfaces for DAP.


Note

ETM and MTB are mutually exclusive. Either ETM, MTB, or none of the two is implemented.

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