5.2. NVIC register summary

Table 5.1 shows the NVIC registers. Each of these registers is 32 bits wide.

Table 5.1. NVIC registers

NVIC_ISERnInterrupt Set-Enable Register n.
NVIC_ICERnInterrupt Clear-Enable Register n.
NVIC_ISPRnInterrupt Set-Pending Register n.
NVIC_ICPRnInterrupt Clear-Pending Register n.
NVIC_IABRnInterrupt Active Bit Register n.
NVIC_ITNSn[a]Interrupt Target Non-Secure Register n.
NVIC_IPRnInterrupt Priority Registers n.

[a] Present only when the Security Extension is implemented.


See the ARM®v8-M Architecture Reference Manual for more information about the NVIC registers and their addresses, access types, and reset values.

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