4.2. System control register summary

Table 4.1 gives the system control registers. Each of these registers is 32 bits wide.

Table 4.1. System control registers

NameDescription
SYST_CSR

SysTick Control and Status Register, see the ARM®v8 -M Architecture Register Manual.

If the Security Extension is implemented:

There are two SYST_CSR registers in the Cortex-M23 processor:

  • SYST_CSR_NS for the Non-secure state (optional).

  • SYST_CSR_S for the Secure state.

[a]

If the Security Extension is not implemented:

There is one SYST_CSR register in the Cortex-M23 processor.

SYST_RVR

SysTick Reload Value Register, see the ARM®v8 -M Architecture Register Manual.

If the Security Extension is implemented:

There are two SYST_RVR registers in the Cortex-M23 processor:

  • SYST_RVR_NS for the Non-secure state (optional).

  • SYST_RVR_S for the Secure state.[a]

If the Security Extension is not implemented:

There is one SYST_RVR register in the Cortex-M23 processor.

SYST_CVR

SysTick Current Value Register, see the ARM®v8 -M Architecture Register Manual.

If the Security Extension is implemented:

There are two SYST_CVR registers in the Cortex-M23 processor:

  • SYST_CVR_NS for the Non-secure state (optional).

  • SYST_CVR_S for the Secure state.[a]

If the Security Extension is not implemented:

There is one SYST_CVR register in the Cortex-M23 processor.

SYST_CALIB[b]

SysTick Calibration value Register, see the ARM®v8 -M Architecture Register Manual.

If the Security Extension is implemented:

There are two SYST_CALIB registers in the Cortex-M23 processor:

  • SYST_CALIB_NS for the Non-secure state (optional).

  • SYST_CALIB_S for the Secure state.[a]

If the Security Extension is not implemented:

There is one SYST_CALIB register in the Cortex-M23 processor.

CPUIDSee CPUID Register.
ICSRInterrupt Control and State Register, see the ARM®v8-M Architecture Reference Manual.
AIRCR[b] Application Interrupt and Reset Control Register, see the ARM®v8-M Architecture Reference Manual.
CCR Configuration and Control Register, see the ARM®v8-M Architecture Reference Manual.
SHPR2System Handler Priority Register 2, see the ARM®v8-M Architecture Reference Manual.
SHPR3System Handler Priority Register 3, see the ARM®v8-M Architecture Reference Manual.
SHCSR System Handler Control and State Register, see the ARM®v8-M Architecture Reference Manual.
VTOR[c]

Vector table Offset Register, see the ARM®v8 -M Architecture Register Manual.

If the Security Extension is implemented:

There are two VTOR registers in the Cortex-M23 processor:[d]

  • VTOR_NS for the Non-secure state (optional).

  • VTOR_S for the Secure state (optional).

If the Security Extension is not implemented:

There is one VTOR register in the Cortex-M23 processor (optional).

ACTLRSee ACTLR Register.

[a] If there is only one SysTick timer present, it is configurable by software if this register is Secure or not.

[b] This value is configured by the implementer during implementation. See the documentation that is supplied by your vendor for more information.

[c] The initial value of VTOR is determined by external input pins on the processor's top level. This determines the vector table that is used for boot up sequence.

If implemented, the VTOR enables bits[31:8] of the vector table address to be specified. The reset value can be configured by external pins. Bits[9:8] can be RAZ/WI depending on the number of interrupts.

If not implemented, the registers are RO/WI and report the value of the external pins.

[d] There is no option to have only one VTOR register if the Security Extension is implemented.


Note

  • All system control registers are only accessible using word transfers. Any attempt to read or write a halfword or byte generates a Hardfault.

  • If the processor is implemented without the SysTick timers, the SYST_CSR, SYST_RVR, SYST_CVR, and SYST_CALIB registers are RAZ/WI.

  • If the processor is implemented with a single SysTick timer, the SYST_CSR_NS, SYST_RVR_NS, SYST_CVR_NS, and SYST_CALIB_NS registers are RAZ/WI.

  • See the ARM®v8-M Architecture Reference Manual for more information about the system control registers, and their addresses and access types, and reset values that are not shown in Table 4.1.

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