5.1.1. Low-power modes

The processor fully implements the Wait For Interrupt (WFI), Wait For Event (WFE) and the Send Event (SEV) instructions. In addition, the processor also supports the use of SLEEPONEXIT, that causes the processor core to enter sleep mode when it returns from an exception handler to Thread mode. The SLEEPONEXIT is banked depending on the security states.

The implementation can include a WIC. This enables the processor and NVIC to be put into a low-power sleep mode leaving the WIC to identify and prioritize interrupts.

See the ARM®v8-M Architecture Reference Manual for more information.

Copyright © 2016 ARM. All rights reserved.ARM DDI 0550C
Non-ConfidentialID112116