3.4. eFlash cache

The eFlash cache is an instruction cache instantiated between the interconnect and the eFlash controller. The cache interfaces with the interconnect (master) over a 32-bit AHB-Lite bus and interfaces with the eFlash over a 128-bit AHB-Lite bus. The cache maintenance operations are performed through an APB4 interface

Copyright © 2015. All rights reserved.ARM DDI 0551A