ARM IoT Subsystem for Cortex-M Technical Reference Manual: A.6. Bus signals

A.6. Bus signals

The table below lists the signals for the two AHB master interfaces. Not shown in the list is the TARGEXP<0..1> prefix before each signal name.

Table A.13. External AHB target port signals

Name	Direction	Width	Description
HSEL	Output	1	Slave Select.
HADDR	Output	32	Address bus.
HTRANS	Output	2	Transfer Type.
HWRITE	Output	1	Transfer Direction.
HSIZE	Output	3	Transfer Size.
HBURST	Output	3	Burst type.
HPROT	Output	4	Protection Control.
HMASTER	Output	4	Master Select.
HWDATA	Output	32	Write Data.
HMASTLOCK	Output	1	Locked Sequence.
HREADYMUX	Output	1	Transfer done.
HAUSER	Output	1	Address USER signals (Not used by the subsystem Cortex-M3 CPU).
EXREQ	Output	1	Exclusive request.
MEMATTR	Output	2	Memory attributes.
HWUSER	Output	4	Write-data USER signals (Not used by the subsystem Cortex-M3 CPU).
HRDATA	Input	32	Read data bus.
HREADYOUT	Input	1	HREADY feedback.
HRESP	Input	1	Transfer response.
HRUSER	Input	3	Read-data USER signals (Not used by the subsystem Cortex-M3 CPU).
EXRESP	Input	1	Exclusive response.

The table below lists the signals for the two AHB slave interfaces. Not shown in the list is the INITEXP<0..1> prefix before each signal name.

Table A.14. External AHB initiator port signals

Name	Direction	Width	Description
HSEL	Input	1	Slave Select.
HADDR	Input	32	Address bus.
HTRANS	Input	2	Transfer Type.
HWRITE	Input	1	Transfer Direction.
HSIZE	Input	3	Transfer Size.
HBURST	Input	3	Burst type.
HPROT	Input	4	Protection Control.
HMASTER	Input	4	Master Select.
HWDATA	Input	32	Write Data.
HMASTLOCK	Input	1	Locked Sequence.
HAUSER	Input	1	Address USER signals (Not used by the subsystem Cortex M3 CPU).
EXREQ	Input	1	Exclusive Request signal.
MEMATTR	Input	2	Memory Attribute signals.
HWUSER	Input	4	Write-data USER signals (Not used by the subsystem Cortex-M3 CPU).
HRDATA	O	32	Read data bus.
HREADY	Output	1	HREADY feedback.
HRESP	Output	1	Transfer response.
HRUSER	Output	3	Read-data USER signals (Not used by the subsystem Cortex-M3 CPU).
EXRESP	Output	1	Exclusive Response.

The table below lists the signals for the two APB slave interfaces. Not shown in the list is the APBTARGETEXP<n> prefix before each signal name, where n is 2, 4, 5, 6, 7, 8, 11, 12, 13, 14, or 15.

Table A.15. External APB target port signals

Name	Direction	Width	Description
PSEL	Output	1	Slave select signal.
PENABLE	Output	1	Strobe to time all accesses. Used to indicate the second cycle of an APB transfer.
PADDR	Output	12 [11:0]	Address bus.
PWRITE	Output	1	APB transfer direction.
PWDATA	Output	32	32-bit write data bus.
PRDATA	Input	32	32-bit read data bus.
PREADY	Input	1	Driven LOW if extra wait states are required to complete the transfer.
PSLVERR	Input	1	Indicates SLVERR response.
PSTRB	Output	1	Write strobes. This signal indicates which byte lanes to update during a write transfer. There is one write strobe for each eight bits of the write data bus. PSTRB[n] corresponds to PWDATA[(8n + 7):(8n)]. Write strobes must not be active during a read transfer
PPROT	Output	3	Protection type. This signal indicates the normal, privileged, or secure protection level of the transaction and whether the transaction is a data access or an instruction access.

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