A.6. Bus signals

The table below lists the signals for the two AHB master interfaces. Not shown in the list is the TARGEXP<0..1> prefix before each signal name.

Table A.13. External AHB target port signals

NameDirectionWidthDescription
HSELOutput1Slave Select.
HADDROutput32Address bus.
HTRANSOutput2Transfer Type.
HWRITEOutput1Transfer Direction.
HSIZEOutput3Transfer Size.
HBURSTOutput3Burst type.
HPROTOutput4Protection Control.
HMASTEROutput4Master Select.
HWDATAOutput32Write Data.
HMASTLOCKOutput1Locked Sequence.
HREADYMUXOutput1Transfer done.
HAUSEROutput1Address USER signals (Not used by the subsystem Cortex-M3 CPU).
EXREQOutput1Exclusive request.
MEMATTROutput2Memory attributes.
HWUSEROutput4Write-data USER signals (Not used by the subsystem Cortex-M3 CPU).
HRDATAInput32Read data bus.
HREADYOUTInput1HREADY feedback.
HRESPInput1Transfer response.
HRUSERInput3Read-data USER signals (Not used by the subsystem Cortex-M3 CPU).
EXRESPInput1Exclusive response.

The table below lists the signals for the two AHB slave interfaces. Not shown in the list is the INITEXP<0..1> prefix before each signal name.

Table A.14. External AHB initiator port signals

NameDirectionWidthDescription
HSELInput1Slave Select.
HADDRInput32Address bus.
HTRANSInput2Transfer Type.
HWRITEInput1Transfer Direction.
HSIZEInput3Transfer Size.
HBURSTInput3Burst type.
HPROTInput4Protection Control.
HMASTERInput4Master Select.
HWDATAInput32Write Data.
HMASTLOCKInput1Locked Sequence.
HAUSERInput1Address USER signals (Not used by the subsystem Cortex M3 CPU).
EXREQInput1Exclusive Request signal.
MEMATTRInput2Memory Attribute signals.
HWUSERInput4Write-data USER signals (Not used by the subsystem Cortex-M3 CPU).
HRDATAO32Read data bus.
HREADYOutput1HREADY feedback.
HRESPOutput1Transfer response.
HRUSEROutput3Read-data USER signals (Not used by the subsystem Cortex-M3 CPU).
EXRESPOutput1Exclusive Response.

The table below lists the signals for the two APB slave interfaces. Not shown in the list is the APBTARGETEXP<n> prefix before each signal name, where n is 2, 4, 5, 6, 7, 8, 11, 12, 13, 14, or 15.

Table A.15. External APB target port signals

NameDirectionWidthDescription
PSELOutput1Slave select signal.
PENABLEOutput1Strobe to time all accesses. Used to indicate the second cycle of an APB transfer.
PADDROutput12 [11:0]Address bus.
PWRITEOutput1APB transfer direction.
PWDATAOutput3232-bit write data bus.
PRDATAInput3232-bit read data bus.
PREADYInput1Driven LOW if extra wait states are required to complete the transfer.
PSLVERRInput1Indicates SLVERR response.
PSTRBOutput1

Write strobes. This signal indicates which byte lanes to update during a write transfer. There is one write strobe for each eight bits of the write data bus.

PSTRB[n] corresponds to PWDATA[(8n + 7):(8n)].

Write strobes must not be active during a read transfer

PPROTOutput3Protection type. This signal indicates the normal, privileged, or secure protection level of the transaction and whether the transaction is a data access or an instruction access.

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