A.1. Clock and reset signals

The table below lists clock and reset signals in the IoT Subsystem interface.

Table A.1. Clocks and resets

NameDirectionWidthDescription
AHB2APBHCLKInput1AHB to APB bridge Clock
CPU0CTICLKInput1Clock for the CoreSight CTI. When active, this must be the same clock as CPU0FCLK.
CPU0CTICLKENInput1An enable signal for CPU0CTICLK.
CPU0CTIRESETnInput1Resets the CTI trigger interface and CTI wrapper. De-assert the reset synchronously to CPU0CTICLK.
CPU0DAPCLKInput1A clock signal for the debug bus interface from the Debug Port (DP) component, for example SWJ-DP. This can be asynchronous to other clock signals
CPU0DAPCLKENInput1An enable signal for CPU0DAPCLK
CPU0DAPRESETnInput1Resets the debug bus connected to the AHB-AP inside the Cortex-M3 processor,
CPU0FCLKInput1A free-running clock. This must be active when the processor is running, for debugging, and for the Nested Vectored Interrupt Controller (NVIC) to detect interrupts. The IoT Subsystem implements the WIC with LATCH thus during WIC based sleep it can be gated
CPU0HCLKInput1A system clock. This must be the same as CPU0FCLK when active. You can gate this off when the processor is in sleep
CPU0PORESETnInput1Power-on reset. Resets the entire Cortex-M3 system and debug components, but excluding the CTI trigger interface and CTI wrapper.
CPU0STCALIBInput26Calibration signal for alternative clock source of SysTick timer
CPU0STCLKInput1Clock enable of the alternative clock source of SysTick timer. CPU0STCLK CPU0FCLK is gated with this CPU0STCLK
CPU0SYSRESETnInput1System Reset. Resets the processor and the WIC excluding debug logic in the NVIC, FPB, DWT, and ITM.
DAPNTRSTInput1

Debug nTRST reset initializes the state of the SWJ-DP TAP controller. This reset is typically used by the RealView® ICE module for hot-plug connection of a debugger to a system. It initializes the SWJ-DP controller without affecting the normal operation of the processor.

DAPSWCLKTCKInput1Serial wire clock and JTAG Test clock. Can be asynchronous.
DAPNPOTRSTInput1Debug port power on reset. Deassertion must be synchronized to SWCLKTCK.
FCACHEHCLKInput1AHB Bus clock. This clock is used for all always on logic
FCACHEPCLKGInput1Gated clock input for register interface (APB). It must be the same frequency and same phase as FCACHEHCLK. Can be gated, when there are no APB activities. It is expected to run while APB interface PSEL signal is asserted
FLSEXTCLKInput1Low speed clock input (for example 32KHz) for program/erase operation. This input is used only if the FLS_EXTCLKEN parameter is set to high.
FLSHCLKInput1AHB clock of eFlash controller.
FLSHRESETnInput1De-assert the reset synchronously to FLSHCLK.
FLSPCLKGInput1

FLSPCLKG clock is used for APB interface and the register block that contains the SW writeable registers. FLSPCLKG can be dynamically turned off by APB subsystem controller.

FLSPCLKG must be synchronous to FLSHCLK whenever the two clocks are on at the same time.

FLSPORESETnInput1Power-On-Reset for the eFlash controller. Triggering the in-built self-repair operation of the eFlash Controller to repair eFlash pages and the eFuse values are read and FLSEFUSE is updated. De-assert the reset synchronously to FLSHCLK.
MTXHCLKInput1AHB matrix interconnect clock
MTXHRESETnInput1AHB matrix interconnect reset.
SRAM<0..3>HCLKInput1AHB clock of the SRAM bridges.
TIMER0PCLKInput1The free running clock used for timer operation. This must be the same frequency as, and synchronous to, the TIMER0PCLKG signal.
TIMER0PCLKGInput1APB register read or write logic that permits the clock to peripheral register logic to stop when there is no APB activity.
TIMER0PRESETnInput1De-assert the reset synchronously to TIMER0PCLK.
TIMER1PCLKInput1The free running clock used for timer operation. This must be the same frequency as, and synchronous to, the TIMER1PCLKG signal.
TIMER1PCLKGInput1APB register read or write logic that permits the clock to peripheral register logic to stop when there is no APB activity.
TIMER1PRESETnInput1De-assert the reset synchronously to TIMER0PCLK.
TPIUCLKInput1APB and ATB interface clock.
TPIUTRACECLKINInput1Trace out port source clock.

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