A.4. SRAM signals

The table below lists the interface signals for the AHB2SRAM subsystem.

Table A.11. AHB2SRAM Interfaces

NameDirectionWidthDescription
SRAM<0..3>RDATAInput32SRAM Read data bus.
SRAM<0..3>ADDR Output13SRAM address (word address).
SRAM<0..3>WRENOutput4SRAM Byte write enable. Active HIGH.
SRAM<0..3>WDATAOutput32SRAM Write data.
SRAM<0..3>CSOutput1SRAM Chip select. Active HIGH.

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