A.7.1. DAP signals

The table below lists the interface signals for the DAP subsystem.

Table A.16. DAP

CPU0DAPADDRInput8DAP address bus
CPU0DAPSELInput1Select signal generated from the DAP decoder to each AP. This signal indicates that the slave device is selected, and a data transfer is required. There is a DAPSEL signal for each slave. The decoder monitors the address bus and asserts the relevant DAPSEL
CPU0DAPENABLEInput1This signal is used to indicate the second and subsequent cycles of a DAP transfer from DP to AHB-AP
CPU0DAPWRITEInput1When HIGH indicates a DAP write access from DP to AHB-AP. When LOW indicates a read access
CPU0DAPABORTInput1Aborts the current transfer. The AHB-AP returns DAPREADY HIGH without affecting the state of the transfer in progress in the AHB master port.
CPU0DAPWDATAInput32The write bus is driven by the DP block during write cycles, when DAPWRITE is HIGH.
CPU0DAPRDATAOutput32The read bus is driven by the selected AHB-AP during read cycles, when DAPWRITE is LOW.
CPU0DAPREADYOutput1The AHB-AP uses this signal to extend a DAP transfer
CPU0DAPSLVERROutput1The error response.

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