A.7.4. Secure debug control

The table below lists the interface signals related to secure debug.

Table A.19. Secure debug control signals

Port nameDirectionWidthDescription

External debug enable.

If CPU0DBGEN is de-asserted, the halt debugging feature of the processor is disabled and the invasive debug features on the CTI are also disabled.

If CPU0DBGEN is asserted, you can use debug features, but you must set other enables, C_DEBUGEN for example, to enable debug events such as halt to occur. Either tie HIGH or connect to a debug access controller if required.

CPU0NIDENInput1Non Invasive debug enable. NIDEN must be HIGH to enable the ETM trace unit to trace instructions.

Input AHB-AP enable. Enables the AHB-AP memory access functionality.

In a typical arrangement, you can tie this signal HIGH. Connect HIGH when enabling debug accesses.

If this signal is LOW, the debugger can still access registers inside the AHB-AP module inside the Cortex-M3 processor, but cannot access the memory map using the AHB interface.


The AHB-AP can issue AHB transactions with a HMASTER value of either 1, to indicate DAP, or 0, to indicate processor data side, depending on how the AHB-AP is configured using the MasterType bit in the AHB-AP Control and Status Word Register.

You can use FIXMASTERTYPE to prevent this if required. If it is tied to 0b1, then the HMASTER that the AHB-AP issues is always 1, to indicate DAP, and it cannot imitate the processor. If it is tied to 0b0, then HMASTER can be issued as either 0 or 1.

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