A.7.5. CPU PPB expansion signals

The table below lists the PPB interface signals related to the DAP subsystem.

Table A.20. CPI0 PPB expansion

CPU0PREADYInput1Bus slave ready.
CPU0PSLVERRInput1Slave response.
CPU0PRDATAInput32Read data.
CPU0PADDROutput31Connect bits [19:2] to PADDR[19:2] from the Cortex-M3 processor.
CPU0PADDR31Output1Indicates whether the transfer originates from the processor (0) or the debugger (1).
CPU0PWRITEOutput1If this is 1, it indicates that the transfer is a write operation.
CPU0PENABLEOutput1This ENABLE signal indicates the second and subsequent cycles of an APB transfer.
CPU0PSELEXTOutput1PSEL for external PPB. This excludes the debug components inside the PIL.
CPU0PWDATAOutput32Write data.

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