A.5. Timer signals

The tables below lists the interface signals for the timer subsystem.

Table A.12. Timer

NameDirectionWidthDescription
TIMER0EXTINInput1Timer0 external input. The external clock. This must be slower than half of the TMER0PCLK clock because it is sampled by a double flip-flop and then goes through edge-detection logic when the external inputs act as a clock.
TIMER1EXTINInput1Timer0 external input. The external clock, must be slower than half of the TMER1PCLK clock because it is sampled by a double flip-flop and then goes through edge-detection logic when the external inputs act as a clock.
TIMER0PRIVMODENInput1Defines if the timer memory mapped registers are writeable only by privileged access.
TIMER1PRIVMODENInput1Defines if the timer memory mapped registers are writeable only by privileged access.
TIMER0TIMERINTOutput1Timer0 interrupt output,
TIMER1TIMERINTOutput1Timer1 interrupt output

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