A.7.3. CPU debug signals

The table below lists the interface signals related to CPU debug.

Table A.18. CPU debug signals

CPU0EDBGRQInput1External debug request. Combined debug request from ETM trace unit and multiprocessor debug support to connect to CoreSight Embedded Cross Trigger. This signal must be synchronous to CPU0FCLK.
CPU0ETMDBGREQOutput1Debug request from ETM
CPU0DBGRESTARTInput1External restart request. The processor exits the halt state when the CPU0DBGRESTART signal is de-asserted during 4-phase handshaking.
CPU0DBGRESTARTEDOutput1Handshake for CPU0DBGRESTART. Devices driving CPU0DBGRESTART must observe this signal to generate the required 4-phase handshaking.
CPU0CTICHINInput4Debug event channel inputs.
CPU0CTICHOUT,Output4Debug event channel inputs.
CPU0CTIASICCTLOutput8ASIC auxiliary control from CTI.

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