A.7.6. Trace signals

The table below lists the HTM interface signals for the Trace subsystem.

Table A.21. HTM signals

NameDirectionWidthDescription
CPU0HTMDHADDROutput32HTM data.
CPU0HTMDHTRANSOutput2HTM data.
CPU0HTMDHSIZEOutput3HTM data.
CPU0HTMDHBURSTOutput3HTM data.
CPU0HTMDHPROTOutput4HTM data.
CPU0HTMDHWDATAOutput32HTM data.
CPU0HTMDHWRITEOutput1HTM data.
CPU0HTMDHRDATAOutput32HTM data.
CPU0HTMDHREADYOutput1HTM data.
CPU0HTMDHRESPOutput2HTM data.
CPU0INTERNALSTATEOutput149Enables the internal operation of core to be observed. OBSERVATION must be implemented to enable this signal to be used.

Table A.22. CPU trace signals

NameDirectionWidthDescription
CPU0TSVALUEBInput48Global timestamp value.
CPU0TSCLKCHANGEInput1Timestamp clock ratio change
CPU0ETMFIFOFULLOutput1ETMFIFOFULL is asserted when the ETM FIFO reaches a watermark.
CPU0ETMINTNUMOutput9Marks the interrupt number of the current execution context.
CPU0ETMINTSTATOutput3Interrupt status.
CPU0ATBYTESETMOutput2ATB number of valid bytes, LSB aligned, Always tied to 0 to indicate the byte size
CPU0AFREADYETMOutput1ATB data flush complete. This is a flush acknowledge. Asserted when buffers are flushed.
CPU0ATREADYETMInput1Transfer destination ready for ETM.
CPU0ATREADYITMInput1Transfer destination ready for ITM.
CPU0TPIUBAUDInput1Unsynchronized baud indicator from TPIU.
CPU0TPIUACTVInput1TPIU has data.
CPU0ATIDETMOutput7ID value for trace source.
CPU0ATVALIDETMOutput1Transfer data valid.
CPU0ATDATAETMOutput8Transfer data.
CPU0ATIDITMOutput7ID value for trace source.
CPU0ATVALIDITMOutput1Transfer data valid.
CPU0ATDATAITMOutput8Transfer data.
CPU0ATBYTESITMOutput2Transfer size (fixed to b00).
CPU0AFREADYITMOutput1ATB flush ready.
CPU0ETMTRIGOUTOutput1Trigger output from ETM (to TPIU).
CPU0DSYNCOutput1Synchronization trigger from DWT to Cortex-M3 TPIU Ignore if using CoreSight TPIU.

The table below lists the interface signals for the Trace Port Interface Unit.

Table A.23. TPIU clock reset and control

NameDirectionWidthDescription
TPIUTRACECLKINInput1Trace out port source clock.
TPIUTRESETnInput1Trace out port active-LOW reset. This is asynchronously asserted and must be synchronously de-asserted to TPIUTRACECLKIN.
TPIUCLKInput1APB and ATB interface clock.
TPIUCLKENInput1Clock enable for TPIUCLK.
TPIUTRACECLKOutput1Output clock, used by the TPA to sample the other pins of the trace out port. This runs at half the speed of TPIUTRACECLKIN, and data is valid on both edges of this clock (clock derived from TPIUTRACECLKIN).
TPIUTRACEDATA[3:0]Output1Output data. A system might not connect all the bits of this signal to the trace port pins, depending on the number of pins available and the bandwidth required to output trace.
TPIUTRACESWOOutput1Serial Wire Viewer data.
TPIUSWOACTIVEOutput1

Controls the multiplexor if SWO shared with TRACEDATA[0].

ARM recommends implementing SWO shared with JTAG-TDO, therefore this pin shall be left unconnected.


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