A.8.2. Power management signals

The table below lists the power-management signals for the debug subsystem. See also Debug and Trace signals.Debug and Trace signals

Table A.25. Debug power-management signals

Signal nameDirectionClockDescription
DAPCDBGPWRUPREQOutputDAPSWCLKTCKActive HIGH signal that indicates an external debugger request to the PMU to power-up the debug domain. This signal must be synchronized before use.
DAPCDBGPWRUPACKInputAsynchronous

Active HIGH signal that indicates the debug domain is powered up in response to DAPCDBGPWRUPREQ being HIGH.

This signal is re-synchronized internally to DAPSWCLKTCK.

DAPCSYSPWRUPREQOutputDAPSWCLKTCKActive HIGH signal that indicates an external debugger request to the PMU to power-up the debug domain. This signal must be synchronized before use.
DAPCSYSPWRUPACKInputAsynchronous

Active HIGH signal that indicates the debug domain is powered up in response to DAPCSYSPWRUPREQ being HIGH.

This signal is re-synchronized internally to DAPSWCLKTCK.

DAPNCDBGPWRDNInputAsynchronousDebug infrastructure power-down control. Controls the clamps of the DAPAPB interface.
DAPCDBGRSTREQOutputDAPSWCLKTCKActive HIGH signal that indicates an external debugger requested a debug reset to reset the controller This signal must be synchronized before use.
DAPCDBGRSTACKInputAsynchronousActive HIGH signal that indicates the debug domain is reset has completed This signal is re-synchronized internally by DAPSWCLKTCK.

The table below lists the power-management signals for the interconnect subsystem. See also Bus signalsBus signals.

Table A.26. Interconnect power-management signals

Signal nameDirectionClockDescription
APBQACTIVEOutputMTXHCLKAPB bus active signal for global clock gating control of all APB peripherals attached to the IoT Subsystem that supports gated APB clock.
TIMER0PCLKQACTIVEOutputMTXHCLKAPB bus active signal for clock gating control of Timer 0 APB clock TIMER0PCLKG (for example PSEL).
TIMER1PCLKQACTIVEOutputMTXHCLKAPB bus active signal for clock gating control of Timer 1 APB clock TIMER1PCLKG (i.e. PSEL).
FLSPCLKQACTIVEOutputMTXHCLKAPB bus active signal for clock gating control of eFlash Controller APB clock FLSPCLKG (for example PSEL).
FCACHEPCLKQACTIVEOutputMTXHCLKAPB bus active signal for clock gating control of eFlash cache APB clock FCACHEPCLKG.
APBTARGEXPnPSELOutputMTXHCLKExternal APB TARGET SEL signals (APB Slave interface).

The table below lists the power-management signals for the eFlash subsystem. See also eFlash signals.

Table A.27. eFlash and eFlash cache power-management signals

Signal nameDirectionClockDescription
FLSSHUTDOWNREQnInputAsynchronous

Powered-up and power-down requests.

Internally synchronized to FLSHCLK.

FLSSHUTDOWNACKnOutputFLSHCLKPower-down acknowledge from the eFlash controller for the eFlash banks.
FCACHERAMPWRUPREQOutputFCACHEHCLKThe eFlash cache module indicates to the PMU to requests power up the DATA and TAG RAM (from either power down or retention).
FCACHERAMPWRUPACKInputAsynchronous

Acknowledge from the PMU that eFlash cache RAMs are powered-up and ready to use.

Internally synchronized to FCACHEHCLK.


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