A.8.1. CPU status and control signals

The table below lists the status and control signals for the CPU subsystem.

Table A.24. CPU control and status

CPU0HALTEDOutput1In halting mode debug. HALTED remains asserted while the core is in debug.
CPU0MPUDISABLEInput1If asserted the MPU is invisible and unusable. Tie HIGH to disable the MPU. Tie LOW to enable the MPU, if present.
CPU0ETMFIFOFULLENInput1Enable ETM FIFIO FULL feature (stall processor when ETM FIFO is full).
CPU0SLEEPINGOutput1Indicated that the processor is in sleep mode (sleep mode).
CPU0SLEEPDEEPOutput1Indicates that the processor is in deep sleep mode.
CPU0SLEEPHOLDREQnInput1Request to extend sleep. Can only be asserted when CPU0SLEEPING is HIGH.
CPU0WAKEUPOutput1Active-HIGH signal to the PMU that indicates that a wake-up event has occurred and the processor system domain requires its clocks and power to be restored.
CPU0WICSENSEOutputImplementation definedActive HIGH set of signals. These indicate the input lines that cause the WIC to generate the WAKEUP signal. (optional, for testing).
CPU0WICENREQInput1Active-HIGH request for deep sleep to be WIC-based deep sleep. The PMU drives this.
CPU0WICENACKOutput1Active-HIGH acknowledge signal for WICENREQ. If you do not require PMU, then tie this signal HIGH to enable the WIC if the WIC is implemented.
CPU0TRCENAOutput1Active HIGH signal that indicates an Trace is Enabled maybe used to gate TPIUCLK.
CPU0ETMENOutput1Active HIGH signal that indicates ETM is enabled maybe used to gate TPIUCLK.
CPU0SYSRESETREQOutput1Processor control - system reset request. AIRC.SYSRESETREQ MMR controls this bit.
CPU0LOCKUPOutput1Indicates that the core is locked up.
CPU0BRCHSTATOutput4Branch status in decode.

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