A.2. Interrupt signals

The table below lists clock and reset signals in the IoT Subsystem interface.

Table A.2. Interrupt signals

NameDirectionWidthDescription
CPU0INTISR[239:0]Input240External interrupt signals. The number of functional interrupt signals depends on your implementation. The Cortex-M3 processor does not implement synchronizers for the CPU0INTISR input. To use asynchronous interrupts, you must implement external synchronizers to reduce the possibility of metastability issues.
CPU0INTNMIInput1Non-mask able Interrupt. The number of functional interrupt signals depends on your implementation. The Cortex-M3 processor does not implement synchronizers for the CPU0INTNMI input. To use asynchronous interrupts, you must implement external synchronizers to reduce the possibility of metastability issues. If the input is connected to an IO pad, a noise filter must be applied.
CPU0CURRPRI[7:0]Output8Indicates what priority interrupt, or base boost, is being used. CURRPRI represents the pre-emption priority, and does not indicate secondary priority.
CPU0AUXFAULT[31:0]Input32Auxiliary fault status information from the system.
CPU0CTIINTISROutput2CTI Interrupt request to top level CTI to system. Acknowledged by writing to the CTIINTACK register in ISR.

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