2.5. Resets

The IoT Subsystem has no internal reset generation implemented (except that Cortex-M3 CPU can be reset by the internal AIRCR.VECTRESET MMR bit of the NVIC).

All component resets in the IoT Subsystem are connected to the IoT Subsystem boundary and can therefore be reset using reset input signals.

Note

The IoT Subsystem is not designed to handle arbitrary reset patterns. The SoC integration and software must ensure that all resets are cleanly released before functional operation and no software reset is triggered to functioning components.

All resets are active low and asynchronous. External reset synchronization is required to guarantee the clean de-assertion of the resets in sync with the corresponding clocks.

Copyright © 2015. All rights reserved.ARM DDI 0551A
Non-ConfidentialID120415