2.2. Cortex-M3 processor block

The block diagram for the Cortex-M3 processor logic and CoreSight SoC interface is shown in the figure below:

Figure 2.2. Cortex-M3 component

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Note

The default implementation reuses the TPIU and SWJDP from Cortex-M3 package and connects the SWJ-DP and TPIU to the Processor Integration layer. For basic usage, there is no requirement to license the CoreSight SoC IP.

The system designer can however choose to design a system with the separately licensed CoreSight SoC debug interface connected to the AHB-AP. In this case the SWJ/DP and TPIU blocks and their corresponding signals are not present.

For more information on the Cortex-M3 and the debug and trace logic, see the following documents:

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