2.10. Debug and Trace

The SWJ-DP is a combined JTAG-DP and SW-DP that enables you to connect either an SWD or JTAG probe to a target. It is the standard CoreSight debug port.

To make efficient use of package pins, the JTAG pins use an auto-detect mechanism that switches between JTAG-DP and SW-DP depending on which probe is connected.

The Cortex-M3 TPIU is an optional component that acts as a bridge between the on-chip trace data from the Embedded Trace Macrocell (ETM) and the Instrumentation Trace Macrocell (ITM), with separate IDs, to a data stream. The TPIU encapsulates IDs where required, and the data stream is then captured by a Trace Port Analyzer (TPA). The Cortex-M3 TPIU is specially designed for low-cost debug.

Note

The default implementation reuses the TPIU and SWJ/DP from the Cortex-M3 package. This configuration is sufficient for basic use.

For more sophisticated multi-processor debug solution, a full CoreSight SoC IP solution can be licensed and implemented. If the CoreSight SoC option is selected, the TPIU and SWJ/DP blocks and corresponding interface signals are not present.

See also Debug and Trace signals.

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