A.3.1. Flash cache

The table below lists the interrupt signals for the Flash cache subsystem.

Table A.3. eFlash interrupts

NameDirectionWidthDescription
FCACHEIRQOutput1eFlash cache interrupt output

The table below lists the SRAM signals for the eFlash subsystem.

Table A.4. eFlash cache DATA SRAM Interfaces

NameDirectionWidthDescription
FCACHERAMCLD<0..1>ADDROutputImplementation definedParametrized width data address bus.
FCACHERAMCLD<0..1>WEOutput1Write control for 128 bits (same cycle as address).
FCACHERAMCLD<0..1>RDOutput4Read control per word (same cycle as address).
FCACHERAMCLD<0..1>CSOutput4Chip select per word (same cycle as address).
FCACHERAMCLD<0..1>WDATAOutput128Write data (same cycle as address).
FCACHERAMCLD<0..1>RDATAInput128Read data (1 cycle after address).

The table below lists the statistics signals for the eFlash subsystem.

Table A.5. eFlash cache statistics

NameDirectionWidthDescription
FCACHECACHEMISSOutput1Active high single cycle pulses indicating that a cache miss happened during cache look up.
FCACHECACHEHITOutput1Active high single cycle pulses indicating that a cache hit happened during cache look up

The table below lists the TAG SRAM signals for the eFlash subsystem.

Table A.6. eFlash cache TAG SRAM Interfaces

NameDirectionWidthDescription
FCACHERAMTAG<0..1>ADDROutputImplementation definedParametrized width data address bus
FCACHERAMTAG<0..1>WEOutput1Write control (same cycle as address)
FCACHERAMTAG<0..1>RDOutput1Read control (same cycle as address)
FCACHERAMTAG<0..1>CSOutput1Chip select (same cycle as address)
FCACHERAMTAG<0..1>WDATAOutputImplementation definedWrite data (same cycle as address)
FCACHERAMTAG<0..1>RDATAInputImplementation definedRead data (1 cycle after address)

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