A.3.2. Flash controller

The table below lists the interrupt signals for the Flash controller subsystem.

Table A.7. eFlash interrupts

NameDirectionWidthDescription
FLSIRQOutput1eFlash controller interrupt output

The table below lists the controller signals for the eFlash subsystem.

Table A.8. TSMC eFlash Controller

NameDirectionWidthDescription
FLSEFUSEOutput32eFuse output values
FLSEXTCLKInput1Low speed clock input (for example 32KHz) for program/erase operation. This input is used only if FLS_EXTCLKEN parameter is set to high value.
FLSFACTORYRESETnInput1Completely erase the eFlash contents and reset the eFlash emulated eFuses.
FLSREADYOutput1The Built-in Self Repair is done the redundancy pages are mapped. The fuse values are ready after reset removal.
FLSOBSERVATIONOutput32Additional status signals for test
FLSSAFESTATEACKnOutput1Asserted as a response to FLSSAFESTATEREQn when none of the flash macros are executing any operation which requires high voltage state.
FLSSAFESTATEREQnInput1When asserted it prevents starting any high voltage operation of the flash banks by masking the CTRL register’s WRITE, ROW_WRITE, ERASE, MASS_ERASE bits.

The table below lists the eFlash0 interface signals that are specific to the TSMC 55ULP-TV2 process.

Table A.9. eFlash0 interface

NameDirectionWidthDescription
FLSXADR0OutputImplementation definedX address input, access rows, XADR[2:0] select one row within a page of main memory block or information block.
FLSYADR0Output5Y address input, access data within a row.
FLSDOUT0Input128Data output bus.
FLSDIN0Output128Data input bus.
FLSXE0Output1X address enable, all rows are disabled when XE=0.
FLSYE0Output1Y address enable, YMUX is disabled when YE=0.
FLSSE0Output1Sense amplifier enable.
FLSIFREN0Output1Information block enable.
FLSERASE0Output1Defines erase cycle.
FLSMAS10Output1Defines mass erase cycle, erase whole block.
FLSPROG0Output1Defines program cycle.
FLSNVSTR0Output1Defines non-volatile store cycle.
FLSIFREN10Output1Repaired page/status information read-only access enable.
FLSREDEN0Output1Redundancy page enable for read, program and erase.

The table below lists the eFlash1 interface signals that are specific to the TSMC 55ULP-TV2 process.

Table A.10. eFlash1 interface

NameDirectionWidthDescription
FLSXADR1OutputImplementation definedX address input, access rows, XADR[2:0] select one row within a page of main memory block or information block.
FLSYADR1Output5Y address input, access data within a row.
FLSDOUT1Input128Data output bus.
FLSDIN1Output128Data input bus.
FLSXE1Output1X address enable, all rows are disabled when XE=0.
FLSYE1Output1Y address enable, YMUX is disabled when YE=0.
FLSSE1Output1Sense amplifier enable.
FLSIFREN1Output1Information block enable.
FLSERASE1Output1Defines erase cycle.
FLSMAS11Output1Defines mass erase cycle, erase whole block.
FLSPROG1Output1Defines program cycle.
FLSNVSTR1Output1Defines non-volatile store cycle.
FLSIFREN11Output1Repaired page/status information read-only access enable.
FLSREDEN1Output1Redundancy page enable for read, program and erase.

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