2.4.1. Component clocks

The subsystem does not implement architectural clock gating other than the Cortex-M3 and ETM internal gating. The IoT Subsystem is a single clock domain. The component clocks can however be gated by a custom implementation at SoC level.

For a full list of component clocks, see Clock and reset signals.

For a list of power-management related signals, see Power management.

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