3.3.1. eFlash interrupts

The eFlash Controller provides a HW interrupt signal (IRQ) that can be connected to the CPU. Interrupt status register can be used to identify the exact source of the interrupt.

The IRQ output is synchronous to HCLK. The type of interrupt is level interrupt. The active level is high.

The interrupt output will be high if at least one bit of IRQ_MASKED_STATUS register value is 1.

To clear an interrupt, software writes 1 to the corresponding bit of the IRQ_CLR_STATUS register.

eFlash Controller has the following interrupt sources:

READY

Any write or erase operation finished normally.

TIMEOUT

Row-write operation aborted by time out.

NEXT

Row write operation ready to accept the next word.

There is a corresponding bit for each interrupt source in the IRQ_SET_STATUS, IRQ_CLR_STATUS, IRQ_SET_ENA, IRQ_CLR_ENA and IRQ_MASKED_STATUS registers.

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