3.3.3. Register summary

Table 3.4. APB register map for eFlash controller

Register nameTypeWidthReset valueAddress offsetDescription
IRQ_SET_ENARW320x000000000x0000IRQ_SET_ENA register
IRQ_CLR_ENARW320x000000000x0004IRQ_CLR_ENA register
IRQ_SET_STATUSRW320x000000000x0008IRQ_SET_STATUS register
IRQ_CLR_STATUSRW320x000000000x000CIRQ_CLR_STATUS register
IRQ_MASKED_STATUSRO320x000000000x0010IRQ_MASKED_STATUS register
CTRLRW320x000000000x0014CTRL register
STATUSRO320x000000000x0018STATUS register
CONFIG0RW320x0008003F0x001CCONFIG0 register
CONFIG1RW320x000800000x0020CONFIG1 register
CONFIG2RW320x000800000x0024CONFIG2 register
WADDRRW320x000000000x0028WADDR register
WDATARW320x000000000x002CWDATA register
EFUSERO320x000000000x0030EFUSE register
HWPARAMS0RO320x000020110x0034HWPARAMS0 register
HWPARAMS1RO320x0000003F0x0038HWPARAMS1 register
HWPARAMS2RO320x000000000x003CHWPARAMS2 register
HWPARAMS3RO320x000000000x0040HWPARAMS3 register
PIDR4RO320x000000140x0FD0Product ID Register, PIDR4
PIDR5RO320x000000000x0FD4Product ID Register, PIDR5
PIDR6RO320x000000000x0FD8Product ID Register, PIDR6
PIDR7RO320x000000000x0FDCProduct ID Register, PIDR7
PIDR0RO320x000000300x0FE0Product ID Register, PIDR0
PIDR1RO320x000000B80x0FE4Product ID Register, PIDR1
PIDR2RO320x0000000B0x0FE8Product ID Register, PIDR2
PIDR3RO320x000000000x0FECProduct ID Register, PIDR3
CIDR0RO320x0000000D0x0FF0Component ID Register, CIDR0
CIDR1RO320x000000F00x0FF4Component ID Register, CIDR1
CIDR2RO320x000000050x0FF8Component ID Register, CIDR2
CIDR3RO320x000000B10x0FFCComponent ID Register, CIDR3

IRQ_SET_ENA register

Enables, or reads the enable state of interrupts.

RW register at offset 0x0000.

For the non-reserved bits:

  • On reads:

    • 0: interrupt disabled.

    • 1: interrupt enabled.

      If not masked, a HW interrupt generated if the corresponding bit of the IRQ_STATUS register is set.

  • On writes:

    • 0: no effect.

    • 1: enable interrupt.

Table 3.5. IRQ_SET_ENA register

BitsNameDescriptionAccessReset
[31:3]Reserved-RO, RAZ0
[2]NEXT-RW0
[1]TIMEOUT-RW0
[0]READY-RW0

IRQ_CLR_ENA register

Disables, or reads, the enable state of interrupts.

RW register at offset 0x0004.

For the non-reserved bits:

  • On reads:

    • 0: interrupt disabled.

    • 1: interrupt enabled.

      If not masked, a HW interrupt generated if the corresponding bit of the IRQ_STATUS register is set.

  • On writes:

    • 0: no effect.

    • 1: disable interrupt.

Table 3.6. IRQ_SET_ENA register

BitsNameDescriptionAccessReset
[31:3]Reserved-RO, RAZ0
[2]NEXT-RW0
[1]TIMEOUT-RW0
[0]READY-RW0

IRQ_SET_STATUS register

Shows the current raw status of interrupts or sets the status of interrupts.

RW register at offset 0x0008.

For the non-reserved bits:

  • On reads:

    • 0: interrupt not pending.

    • 1: interrupt pending.

  • On writes:

    • 0: no effect.

    • 1: sets the state of the interrupt to pending.

Table 3.7. IRQ_SET_STATUS register

BitsNameDescriptionAccessReset
[31:3]Reserved-RO, RAZ0
[2]NEXTThis interrupt is set by HW during word-write operation whenever HW is ready to accept the next word.RW0
[1]TIMEOUTThis interrupt is set by HW when any row-write operation finished by HW as a result of SW not clearing the NEXT interrupt within the specified time.RW0
[0]READYThis interrupt set by HW when any word-write, row-write, page-erase, mass-erase operation finishes.RW0

IRQ_CLR_STATUS register

Shows the current raw status of interrupts or clears the status of interrupts.

RW register at offset 0x000C.

For the non-reserved bits:

  • On reads:

    • 0: interrupt not pending.

    • 1: interrupt pending.

  • On writes:

    • 0: no effect.

    • 1: clears the pending state of the interrupt.

Table 3.8. IRQ_CLR_STATUS register

BitsNameDescriptionAccessReset
[31:3]Reserved-RO, RAZ0
[2]NEXTThis interrupt is set by HW during word-write operation whenever HW is ready to accept the next word.RW0
[1]TIMEOUT

This interrupt is set by HW when any row-write operation finished by HW as a result of SW not clearing the NEXT interrupt within the specified time.

On reads:

0 = Interrupt is not pending.

1 = Interrupt is pending.

On writes:

0 = No effect.

1 = Clears the pending state of the interrupt.

RW0
[0]READY

This interrupt is set by HW when any word-write, row-write, page-erase, or mass-erase operation finishes.

On reads:

0 = Interrupt is not pending.

1 = Interrupt is pending.

On writes:

0 = No effect.

1 = Clears the pending state of the interrupt.

RW0

IRQ_MASKED_STATUS register

Shows for each interrupt if it is pending and the cause of the interrupt line being asserted.

RO register at offset 0x0010.

  • On reads:

    • 0: interrupt is not causing IRQ line assertion.

    • 1: interrupt is cause of IRQ line assertion. Interrupt is pending and enabled.

Table 3.9. IRQ_MASKED_STATUS register

BitsNameDescriptionAccessReset
[31:3]Reserved-RO, RAZ0
[2]NEXT-RO0
[1]TIMEOUT-RO0
[0]READY-RO0

CTRL register

eFlash control register.

If SAFESTATEREQn or SHUTDOWNREQn is asserted, the eFlash controller will reject any write attempt to this register and respond with an APB ERROR response.

RW register at offset 0x0014.

Table 3.10. CTRL register

BitsNameDescriptionAccessReset
[31:5]Reserved-RO, RAZ0
[4]STOPStop any write or erase operation. High voltage discharge is taken care of by eFlash Controller.RW0
[3]MASS_ERRASEErase all pages of eFlash.RW0
[2]ERASEErase one page of eFlash.RW0
[1]ROW_WRITEWrite one or more words (32 bit) to a row of eFlash (to sequential addresses) during one high voltage period.RW0
[0]WRITEWrite one word (32 bit) of data to eFlash.RW0

STATUS register

Status or read or erase operation.

RO register at offset 0x0018.

Table 3.11. STATUS register

BitsNameDescriptionAccessReset
[31:2]Reserved-RO, RAZ0
[1]LOCK

Write/Erase lock. Lock conditions are SAFESTATEREQn asserted or SHUTDOWNREQn asserted.

0: Write and Erase operations can be executed by the eFlash controller.

1: The eFlash controller will reject any write or erase with an APB ERROR response.

RO1
[0]BUSYeFlash Controller is executing any write or erase operation. Indicates that any eFlash bank is in HV state.RO0

CONFIG0 register

Configuration register.

RW register at offset 0x001C.

Table 3.12. CONFIG0 register

BitsNameDescriptionAccessReset
[31:26]Reserved-RO, RAZ0
[25:16]ER_CLK_COUNT

Erase clock configuration register.

Set the number of clock cells in 1ms period.

(ER_CLK_COUNT+1) * Clock_period > 1ms

Minimum value is the nearest integer that results in a period > 1ms.

The clock source is always EXTCLK. The valid EXTCLK frequency range is 1kHz - 1MHz.

This register is not implemented if EXTCLKEN parameter set to 0 (RAZ).

RWERCLKCOUNTRST
[15:8]WR_CLK_COUNT

Write clock configuration register.

Set the number of clock cells in 1us period.

If EXT_CLK_CONF is 0x0 or 0x1 then(WR_CLK_COUNT * HCLK-period) >= 1us.

If EXT_CLK_CONF is 0x2 then(WR_CLK_COUNT * EXTCLK-period) >= 1us.

RWWRCLKCOUNTRST
[7:6]ETC_CLK_CONF

Write/erase timers source clock configuration.

If EXTCLKEN parameter is set to 0, then this register is tied to 0x0.

0x0 [Internal] External clock not used.

0x1 [Erase] External clock used for erase counters (>1ms). HCLK used for write counters.

0x2 [Write] External clock used for write and erase counters (>1us).

0x3 [Reserved].

RW0x0
[5:0]RD_CLK_CONF

Read clock configuration register.

0x0 Reserved.

0x1 1_cycle_read_mode. This value is allowed only if HALFCLKREAD parameter is set to 1.

Read from flash in 1 clock cycle over AHB interface,Read from flash in 2 clock cycles over APB interface.

0x2-03F normal_read_mode. eFlash read operation requires RD_CLK_COUNT number of HCLK cycles.

RWRDCLKCOUNTRST

CONFIG1 register

Configuration register.

RW register at offset 0x0020.

Table 3.13. CONFIG1 register

BitsNameDescriptionAccessReset
[31:26]TNVHeFlash timing parameter. NVSTR hold time in microseconds.RWTNVH_RST
[23:16]TPROG

eFlash timing parameter. Programming time in microseconds.

RWTPROG_RST
[15:8]TPGS

eFlash timing parameter. NVSTR to program setup time in microseconds.

RWTPGS_RST
[7:0]ETC_CLK_CONF

eFlash timing parameter. PROG or ERASE to NVSTR setup time in microseconds.

RWTNVS_RST

CONFIG2 register

Configuration register.

RW register at offset 0x0024.

Table 3.14. CONFIG2 register

BitsNameDescriptionAccessReset
[31:24]TMEeFlash timing parameter. Mass erase time in ms.RWTME_RST
[23:16]TERASE

eFlash timing parameter. Erase time in ms.

RWTERASE_RST
[15:8]TRCV

eFlash timing parameter. Recovery time in microseconds.

RWTRCV_RST
[7:0]TNVH1

eFlash timing parameter. NVSTR1 hold time in microseconds.

RWTNVH1_RST

WADDR register

Write/Erase address register.

Only word addressing is allowed. Bits [1:0] are tied to 0.

Attempting to write an unmapped address into this register results in an APB ERROR response and the register value is not modified.

It is responsibility of software to ensure that the addressed word of eFlash is in erased state.

The bits have special addressing for information pages:

  • [31]: Select Bank-1 information page.

  • [30]: Select Bank-0 information page.

  • [10:2]: Info page word address offset.

RW register at offset 0x0028.

Table 3.15. WADDR register

BitsNameDescriptionAccessReset
[31:2]WADDR1-RW0
[1:0]Reserved-RO0

WDATA register

Write data register.

RW register at offset 0x002C.

Table 3.16. WDATA register

BitsNameDescriptionAccessReset
[31:0]WDATA-RW0

EFUSE register

Each bit of this register corresponds to an emulated fuse value.

RO register at offset 0x0030.

Table 3.17. EFUSE register

BitsNameDescriptionAccessReset
[31:0]EFUSEEFUSE[0] is efuse 0.RO0

HWPARAMS0 register

Timeout and clock control register. The value of this register is defined by the system designer.

RO register at offset 0x0034.

Table 3.18. HWPARAMS0 register

BitsNameDescriptionAccessReset
[31:16]Reserved-RO, RAZ0
[15:8]TIMEOUTRow-write timeout parameterRO0x20
[7]Reserved-RO, RAZ0
[6]EXTCLKENEnable EXTCLK inputRO0
[5]HALFCLKRDAllow setting RD_CLK_COUNT to 0RO0
[4:0]FLASHSIZEFLASHSIZE parameter = log2(flash size in bytes)RO0x11

HWPARAMS1 register

Clock count parameters. The value of this register is defined by the system designer.

RO register at offset 0x0038.

Table 3.19. HWPARAMS1 register

BitsNameDescriptionAccessReset
[31:26Reserved-RO, RAZ0
[25:12]ERCLKCOUNTRSTReset value of ER_CLK_COUNT register.RO0
[11:4]WRCLKCOUNTRSTReset value of WR_CLK_COUNT register,RO0
[3:0]RDCLKCOUNTRSTReset value of RD_CLK_COUNT register.RO0x3F

HWPARAMS2 register

eFlash timing parameters. The value of this register is defined by the system designer.

RO register at offset 0x003C.

Table 3.20. HWPARAMS2 register

BitsNameDescriptionAccessReset
[31:24]TNVH_RSTeFlash timing parameter. NVSTR hold time in microseconds.RO0
[23:16]TPROG_RSTeFlash timing parameter. Programming time in microseconds. RO0
[15:8]TPGS_RSTeFlash timing parameter. NVSTR to program setup time in microseconds.RO0
[7:0]TNVS_RSTeFlash timing parameter. PROG/ERASE to NVSTR setup time in microseconds.RO0

HWPARAMS3 register

eFlash timing parameters for erase and hold. The value of this register is defined by the system designer.

RO register at offset 0x0040.

Table 3.21. HWPARAMS3 register

BitsNameDescriptionAccessReset
[31:24]TME_RSTeFlash timing parameter. Mass erase time in ms. RO0
[23:16]TERASE_RSTeFlash timing parameter. Erase time in ms.RO0
[15:8]TRCV_RSTeFlash timing parameter. Recovery time in microseconds. RO0
[7:0]TNVH1_RSTeFlash timing parameter. NVSTR1 hold time in microseconds. RO0

Product ID Register, PIDR4

eFlash parameters for address space.

RO register at offset 0x0FD0.

Table 3.22. PIDR4 register

BitsNameDescriptionAccessReset
[31:8]Reserved-RO, RAZ0
[7:4]SIZE8k address spaceRO0x1
[3:0]DES_2JEP 106 continuation codeRO0x4

Product ID Register, PIDR5

Reserved.

RO register at offset 0x0FD4.

Table 3.23. PIDR5 register

BitsNameDescriptionAccessReset
[31:8]Reserved-RO, RAZ0
[7:0]Reserved-RO, RAZ0

Product ID Register, PIDR6

Reserved.

RO register at offset 0x0FD8.

Table 3.24. PIDR6 register

BitsNameDescriptionAccessReset
[31:8]Reserved-RO, RAZ0
[7:0]Reserved-RO, RAZ0

Product ID Register, PIDR7

Reserved.

RO register at offset 0x0FDC.

Table 3.25. PIDR7 register

BitsNameDescriptionAccessReset
[31:8]Reserved-RO, RAZ0
[7:0]Reserved-RO, RAZ0

Product ID Register, PIDR0

eFlash part number.

RO register at offset 0x0FE0.

Table 3.26. PIDR0 register

BitsNameDescriptionAccessReset
[31:8]Reserved-RO, RAZ0
[7:0]PART_0Bits [7:0] of the part number.RO, RAZ0x30

Product ID Register, PIDR1

eFlash part number.

RO register at offset 0x0FE4.

Table 3.27. PIDR1 register

BitsNameDescriptionAccessReset
[31:8]Reserved-RO, RAZ0
[7:4]DES_0Bits [11:8] of the part number.RO, RAZ0xB
[3:0]PART_0Bits [11:8] of the part number.RO, RAZ0x8

Product ID Register, PIDR2

eFlash revision number.

RO register at offset 0x0FE8.

Table 3.28. PIDR2 register

BitsNameDescriptionAccessReset
[31:8]Reserved-RO, RAZ0
[7:4]REVISIONRevision number of the peripheral.RO, RAZ0
[3]JEDECAlways set. Indicates that a JEDEC assigned value is used.RO, RAZ0x1
[2:0]DES_1JEP106 identification code, bits[6:4]RO, RAZ0x3

Product ID Register, PIDR3

eFlash customer-modified number.

RO register at offset 0x0FEC.

Table 3.29. PIDR3 register

BitsNameDescriptionAccessReset
[31:8]Reserved-RO, RAZ0
[7:4]REVANDECO revisionRO, RAZ0
[3:0]CMODCustomer modified numberRO, RAZ0

Component ID Register, CIDR0

eFlash parameter register.

RO register at offset 0x0FF0.

Table 3.30. CIDR0 register

BitsNameDescriptionAccessReset
[31:8]Reserved-RO, RAZ0
[7:0]PRMBL_0-RO0x0D

Component ID Register, CIDR1

eFlash parameter register for IP component.

RO register at offset 0x0FF4.

Table 3.31. CIDR1 register

BitsNameDescriptionAccessReset
[31:8]Reserved-RO, RAZ0
[7:4]CLASSComponent classRO0xF
[3:0]PRMBL_1-RO0x0

Component ID Register, CIDR2

eFlash parameter register.

RO register at offset 0x0FF8.

Table 3.32. CIDR2 register

BitsNameDescriptionAccessReset
[31:8]Reserved-RO, RAZ0
[7:0]PRMBL_2-RO0x05

Component ID Register, CIDR3

eFlash parameter register.

RO register at offset 0x0FFC.

Table 3.33. CIDR3 register

BitsNameDescriptionAccessReset
[31:8]Reserved-RO, RAZ0
[7:0]PRMBL_3-RO0xB1

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