3.4.1. Register summary

The table below summarizes the registers in the eFlash cache.

Table 3.34. eFlash cache registers

Register nameTypeWidthReset ValueAddress OffsetDescription
CCRRW320x000000400x000Configuration and Control Register, CCR
SRRO320x000000000x004Status Register, SR
IRQMASKRW320x000000000x008Interrupt Request Mask register, IRQMASK
IRQSTATRW320x000000000x00CInterrupt Request Status register, IRQSTAT
HWPARAMSRO320x000039920x010Hardware Parameters register, HWPARAMS
CSHRRW320x000000000x014Cache Statistic Hit Register, CSHR
CSMRRW320x000000000x018Cache Statistic Miss Register, CSMR
PIDR4RO320x000000040xFD0Product ID Register, PIDR4
PIDR5RO320x000000000xFD4Product ID Register, PIDR5
PIDR6RO320x000000000xFD8Product ID Register, PIDR6
PIDR7RO320x000000000xFDCProduct ID Register, PIDR7
PIDR0RO320x000000290xFE0Product ID Register, PIDR0
PIDR1RO320x000000B80xFE4Product ID Register, PIDR1
PIDR2RO320x0000000B0xFE8Product ID Register, PIDR2
PIDR3RO320x000000000xFECProduct ID Register, PIDR3
CIDR0RO320x0000000D0xFF0Component ID Register, CIDR0
CIDR1RO320x000000F00xFF4Component ID Register, CIDR1
CIDR2RO320x000000050xFF8Component ID Register, CIDR2
CIDR3RO320x000000B10xFFCComponent ID Register, CIDR3

Configuration and Control Register, CCR

Configuration and control register.

RW register at offset 0x000.

Table 3.35. CCR register

BitsNameDescriptionAccessReset
[31:7]Reserved-RO, RAZ0
6STATISTIC_EN

Enable statistics logic:

0: Disabled. Counters are stalled.

1: Enable. Counters are running.

RW1
5SET_PREFETCH

Cache Prefetch Setting:

0: Disable cache.

1: Enable cache.

RW0
4SET_MAN_INV

Cache Invalidate Setting:

0: Automatic cache invalidate when cache enabled.

1: Manual cache invalidate mode.

RW0
3SET_MAN_POW

Power Control Setting:

0: Automatic.

1: Manual.

RW0
2POW_REQManual SRAM power request. RW0
1INV_REQ

Manual invalidate request.

Functional only when SET_MAN_INV is set. Automatically cleared when invalidation is finished or power or invalidation error occurs. Cannot be cleared manually.

Manual invalidation request should be set only when cache is disabled otherwise it causes invalidation error interrupt.

RW0
0EN

Cache Enable:

0: Disable cache.

1: Enable cache.

RW0

Status Register, SR

Status register.

RO register at offset 0x004.

Table 3.36. SR register

BitsNameDescriptionAccessReset
[31:5]Reserved-RO, RAZ0
4POW_STATSRAM power acknowledges. Real-time registered value of RAMPWRUPACK port.RO0
3Reserved-RO, RAZ0
2INV_STATInvalidating Status. Indicates if invalidation process is ongoing.RO0
[1:0]CS

Cache status:

0: Cache disabled.

1: Cache enabling.

2: Cache enabled.

3: Cache disabling.

RO0

Interrupt Request Mask register, IRQMASK

Interrupt request mask register. Set to 0 to enable interrupts for events, and set to 1 to mask interrupts.

RW register at offset 0x008.

Table 3.37. IRQMASK register

BitsNameDescriptionAccessReset
[31:2]Reserved-RO, RAZ0
1MAN_INV_ERRMask interrupt request on manual invalidation error indication (IRQSTAT.MAN_INV_ERR is set).RW0
0POW_ERRMask interrupt request on Power Error indication (IRQSTAT.POW_ERR is set).RW0

Interrupt Request Status register, IRQSTAT

Interrupt Request Status Register. IRQSTAT register status bits cannot be masked. They are set on the corresponding error event regardless of IRQMASK settings.

RW register at offset 0x00C.

Table 3.38. IRQSTAT register

BitsNameDescriptionAccessReset
[31:2]Reserved-RO, RAZ0
1MAN_INV_ERRManual invalidation error status. Set when manual invalidation is requested meanwhile the cache is not disabled. Write 1 to clear.RW0
0POW_ERR

SRAM power error. Write 1 to clear.

Power acknowledge de-asserted during operation.

Manual power request de-asserted while cache is enabled and operating in manual power mode.

RW0

Hardware Parameters register, HWPARAMS

Hardware parameters register holding implementation-defined parameter values.

RO register at offset 0x010.

Table 3.39. HWPARAMS register

BitsNameDescriptionAccessReset
[31:14]Reserved-RO, RAZ0
13GEN_STAT_LOGICIndicates GEN_STAT_LOGIC hardware parameter value.RO1
12RESET_ALL_REGSIndicates RESET_ALL_REGS hardware parameter value.RO1
[11:10]CACHE_WAY

Implementation-defined value for number of cache ways:

  • 2: Two cache ways.

RO2
[9:5]CW

Implementation-defined value for cache way width:

  • 8: 256B.

  • 9: 512B.

  • 11: 2KB.

  • 12: 4KB.

RO0x0C
[4:0]AW

Implementation-defined value for AHB-Lite bus width for the flash address space:

  • 18: 256KB.

  • 19: 512KB.

RO0x12

Cache Statistic Hit Register, CSHR

Cache Statistic Hit Register.

Including this register in a design is optional. If not present and the register is accessed, a slave OKAY response is given.

RW register at offset 0x014.

Table 3.40. CSHR register

BitsNameDescriptionAccessReset
[31:0]CSHR

Counts the number of cache hits during cache look up.

Only cacheable read transactions are looked up by the eFlash cache.

Writing to the register clears the contents.

RW0

Cache Statistic Miss Register, CSMR

Cache Statistic Miss Register.

Including this register in a design is optional. If not present and the register is accessed, a slave OKAY response is given.

RW register at offset 0x018.

Table 3.41. CMSR register

BitsNameDescriptionAccessReset
[31:0]CSMR

Counts the number of cache misses during cache look up.

Only cacheable read transactions are looked up by the eFlash cache.

Writing to the register clears the contents.

RW0

Product ID Register, PIDR4

Product ID register.

RO register at offset 0xFD0.

Table 3.42. PIDR4 register

BitsNameDescriptionAccessReset
[31:8]Reserved-RO, RAZ0
[7:4]SIZE-RO0x0
[3:0]DES_2JEP 106 continuation codeRO0x4

Product ID Register, PIDR5

Product ID register.

RO register at offset 0xFD4.

Table 3.43. PIDR5 register

BitsNameDescriptionAccessReset
[31:8]Reserved-RO, RAZ0
[7:0]Reserved-RO, RAZ0

Product ID Register, PIDR6

Product ID register.

RO register at offset 0xFD8.

Table 3.44. PIDR6 register

BitsNameDescriptionAccessReset
[31:8]Reserved-RO, RAZ0
[7:0]Reserved-RO, RAZ0

Product ID Register, PIDR7

Product ID register.

RO register at offset 0xFDC.

Table 3.45. PIDR7 register

BitsNameDescriptionAccessReset
[31:8]Reserved-RO, RAZ0
[7:0]Reserved-RO, RAZ0

Product ID Register, PIDR0

Product ID register.

RO register at offset 0xFE0.

Table 3.46. PIDR0 register

BitsNameDescriptionAccessReset
[31:8]Reserved-RO, RAZ0
[7:0]PART_0Part number bits [7:0].RO0x29

Product ID Register, PIDR1

Product ID register.

RO register at offset 0xFE4.

Table 3.47. PIDR1 register

BitsNameDescriptionAccessReset
[31:8]Reserved-RO, RAZ0
[7:4]DES_0PJEP106 identification code bits [3:0].RO0xB
[3:0]PART_1Part number bits [11:8].RO0x8

Product ID Register, PIDR2

Product ID register.

RO register at offset 0xFE8.

Table 3.48. PIDR2 register

BitsNameDescriptionAccessReset
[31:8]Reserved-RO, RAZ0
[7:4]REVISIONRevision number of the peripheralRO0x0
3JEDECAlways set. Indicates that a JEDEC assigned value is used.RO1
[2:0]DES_1JEP106 identification code bits [11:8].RO0x3

Product ID Register, PIDR3

Product ID register.

RO register at offset 0xFEC.

Table 3.49. PIDR3 register

BitsNameDescriptionAccessReset
[31:8]Reserved-RO, RAZ0
[7:4]REVANDECO revision.RO0x0
[2:0]CMODCustomer modified number.RO0x0

Component ID Register, CIDR0

Component ID register.

RO register at offset 0xFF0.

Table 3.50. CIDR0 register

BitsNameDescriptionAccessReset
[31:8]Reserved-RO, RAZ0
[7:0]PRMBL_0-RO0x0D

Component ID Register, CIDR1

Component ID register.

RO register at offset 0xFF4.

Table 3.51. CIDR1 register

BitsNameDescriptionAccessReset
[31:8]Reserved-RO, RAZ0
[7:4]CLASSComponent Class. Returns 0xE for a generic IP component.RO0x0F
[3:0]PRMBL_1-RO0x0

Component ID Register, CIDR2

Component ID register.

RO register at offset 0xFF8.

Table 3.52. CIDR2 register

BitsNameDescriptionAccessReset
[31:8]Reserved-RO, RAZ0
[7:0]PRMBL_2-RO0x05

Component ID Register, CIDR3

Component ID register.

RO register at offset 0xFFC.

Table 3.53. CIDR3 register

BitsNameDescriptionAccessReset
[31:8]Reserved-RO, RAZ0
[7:0]PRMBL_3-RO0xB1

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