3.5.1. Interrupt signals

This section describes interrupts and exceptions handled by the Cortex-M3 in the IoT Subsystem.

Table 3.54. Exceptions

No.Exception type PriorityDescription
1Reset-3Reset is invoked on power up or a warm reset
2NMI-2CPU0INTNMI port input
3Hard-Fault-1A Hard Fault is an exception that occurs because of an error during exception processing
4Memory manage faultProgrammableException from MPU
5Bus faultProgrammableBus error of bus access to the area that is not controlled by the MPU
6Use faultProgrammableError about operating instruction including undefined instruction
7-10Reserved--
11SVCallProgrammableCall
12Debug MonitorProgrammableException that is triggered by the SVC instruction
13Reserved- 
14PendSVProgrammablePendSV is an interrupt-driven request for system-level service
15SysTickProgrammableSysTick exception is an exception the system timer generates when it reaches zero.
16Interrupt SpecificprogrammableAn exception signaled by a peripheral, or generated by a software request.

The reference interrupt table are listed in the table below:

Table 3.55. Interrupts

No.NAME SourceDescription
16CPU0INTISR0FCACHEIRQInterrupt from eFlash cache (Instruction Cache) module.
17CPU0INTISR1FLSIRQInterrupt from the eFlash Controller module.
18CPU0INTISR2TIMER0TIMERINTInterrupt from APB Timer 0 module.
19CPU0INTISR3TIMER1TIMERINTInterrupt from APB Timer 0 module.
20CPU0INTISR4BTTXIRQINTCombined TX interrupt of BT radio.
21CPU0INTISR5BTRXIRQINTCombined RX interrupt of BT radio.
22CPU0INTISR6UART0INTCombined interrupt from APB_UART0 module.
23CPU0INTISR7UART1INTCombined interrupt from APB_UART1 module.
-CPU0INTISR8-31Not used-

Note

The interrupt signals from the peripherals are not connected directly to the interrupt controller. All signals go to the integration layer and might be connected differently by the system designer.

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