ARM® CoreLink™ SSE-100 Subsystem Technical Reference Manual

Revision: r0p0


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Glossary
Conventions
Additional reading
Feedback
Feedback on this product
Feedback on content
1. Introduction
1.1. About IoT endpoints
1.2. Features of the SSE-100
1.3. Compliance
1.3.1. ARM architecture
1.3.2. Interrupt controller architecture
1.3.3. Advanced Microcontroller Bus Architecture
1.4. Product revisions
2. Functional description
2.1. System top-level partitioning
2.2. Cortex-M3 processor block
2.3. Power management
2.4. Clocks
2.4.1. Component clocks
2.5. Resets
2.5.1. Reset inputs
2.5.2. About boot after reset
2.5.3. Events
2.6. Timer
2.6.1. Security extension
2.7. eFlash memory subsystem
2.7.1. eFlash cache
2.7.2. TSMC eFlash controller
2.8. Banked SRAM subsystem
2.9. AHB and APB expansion
2.9.1. APB slave multiplexer
2.9.2. AHB expansion
2.10. Debug and Trace
3. Programmers model
3.1. About this programmers model
3.2. Memory map
3.2.1. Remap
3.2.2. Peripheral, expansion, and system regions
3.3. eFlash controller
3.3.1. eFlash interrupts
3.3.2. APB memory map
3.3.3. Register summary
3.4. eFlash cache
3.4.1. Register summary
3.5. Interrupts
3.5.1. Interrupt signals
3.5.2. Registers
3.6. Wakeup Interrupt Controller (WIC)
3.7. Timer
3.8. System registers
3.9. Debug and Trace
A. Signal descriptions
A.1. Clock and reset signals
A.2. Interrupt signals
A.3. eFlash signals
A.3.1. eFlash cache
A.3.2. eFlash controller
A.4. SRAM signals
A.5. Timer signals
A.6. Bus signals
A.7. Debug and Trace signals
A.7.1. DAP signals
A.7.2. JTAG and SWD signals
A.7.3. CPU debug signals
A.7.4. Secure debug control
A.7.5. CPU PPB expansion signals
A.7.6. Trace signals
A.8. CPU control, status, and power management signals
A.8.1. CPU status and control signals
A.8.2. Power management signals
A.9. Memory remap signals
A.10. DFT signals
B. Revisions

List of Tables

1. Typographical conventions
2.1. Cortex-M3 events 
2.2. Privilege mode enable input signals  
2.3. APB ports 
3.1. Code and SRAM regions
3.2. Expansion and system map
3.3. APB memory map for eFlash controller
3.4. APB register map for eFlash controller
3.5. IRQ_SET_ENA register
3.6. IRQ_SET_ENA register
3.7. IRQ_SET_STATUS register
3.8. IRQ_CLR_STATUS register
3.9. IRQ_MASKED_STATUS register
3.10. CTRL register
3.11. STATUS register
3.12. CONFIG0 register
3.13. CONFIG1 register
3.14. CONFIG2 register
3.15. WADDR register
3.16. WDATA register
3.17. EFUSE register
3.18. HWPARAMS0 register
3.19. HWPARAMS1 register
3.20. HWPARAMS2 register
3.21. HWPARAMS3 register
3.22. PIDR4 register
3.23. PIDR5 register
3.24. PIDR6 register
3.25. PIDR7 register
3.26. PIDR0 register
3.27. PIDR1 register
3.28. PIDR2 register
3.29. PIDR3 register
3.30. CIDR0 register
3.31. CIDR1 register
3.32. CIDR2 register
3.33. CIDR3 register
3.34. eFlash cache registers
3.35. CCR register
3.36. SR register
3.37. IRQMASK register
3.38. IRQSTAT register
3.39. HWPARAMS register
3.40. CSHR register
3.41. CMSR register
3.42. PIDR4 register
3.43. PIDR5 register
3.44. PIDR6 register
3.45. PIDR7 register
3.46. PIDR0 register
3.47. PIDR1 register
3.48. PIDR2 register
3.49. PIDR3 register
3.50. CIDR0 register
3.51. CIDR1 register
3.52. CIDR2 register
3.53. CIDR3 register
3.54. Exceptions
3.55. Interrupts
3.56. Summary of interrupt controller registers
3.57. Summary of timer registers
3.58. Part number ID values
A.1. Clocks and resets
A.2. Interrupt signals
A.3. eFlash interrupts
A.4. eFlash cache DATA SRAM Interfaces
A.5. eFlash cache statistics
A.6. eFlash cache TAG SRAM Interfaces
A.7. eFlash interrupts
A.8. TSMC eFlash Controller
A.9. eFlash0 interface
A.10. eFlash1 interface
A.11. AHB2SRAM Interfaces
A.12. Timer
A.13. External AHB target port signals
A.14. External AHB initiator port signals
A.15. External APB target port signals
A.16. DAP
A.17. JTAG and SW Debug access functional signals
A.18. CPU debug signals
A.19. Secure debug control signals
A.20. CPI0 PPB expansion
A.21. HTM signals
A.22. CPU trace signals
A.23. TPIU clock reset and control
A.24. CPU control and status
A.25. Debug power-management signals
A.26. Interconnect power-management signals
A.27. eFlash and eFlash cache power-management signals
A.28. Memory remap signals
A.29. DFT signals
B.1. Issue A
B.2. Differences between issue A and issue B

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Product Status

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Revision History
Revision A13 November 2015First release for r0p0
Revision B13 October 2016Second release for r0p0
Copyright © 2015, 2016 ARM or its affiliates. All rights reserved.ARM DDI 0551B
Non-ConfidentialID101316