3.3.2. Status Register, SR

Status register.

RO register at offset 0x004.

Table 3.3. SR register

BitsNameDescriptionAccessReset
[31:5]Reserved-RO, RAZ0
4POW_STATSRAM power acknowledges. Real-time registered value of RAMPWRUPACK port.RO0
3Reserved-RO, RAZ0
2INV_STATInvalidating Status. Indicates if invalidation process is ongoing.RO0
[1:0]CS

Cache status:

0: Cache disabled.

1: Cache enabling.

2: Cache enabled.

3: Cache disabling.

RO0

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