3.3.3. Interrupt Request Mask register, IRQMASK

Interrupt request mask register. Set to 0 to enable interrupts for events, and set to 1 to mask interrupts.

RW register at offset 0x008.

Table 3.4. IRQMASK register

BitsNameDescriptionAccessReset
[31:2]Reserved-RO, RAZ0
1MAN_INV_ERRMask interrupt request on manual invalidation error indication (IRQSTAT.MAN_INV_ERR is set).RW0
0POW_ERRMask interrupt request on Power Error indication (IRQSTAT.POW_ERR is set).RW0

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