3.3.7. Cache Statistic Miss Register, CSMR

Cache Statistic Miss Register contains the cache miss count.

Including this register in a design is optional. If not present and the register is accessed, a slave OKAY response is given and the register address is RAZ.

RW register at offset 0x018.

Table 3.8. CMSR register

BitsNameDescriptionAccessReset
[31:0]CSMR

Counts the number of cache misses during cache look up.

Only cacheable read transactions are looked up by the CG092.

Writing to the register clears the contents.

RW0

The count value in the registers saturate at 0xFFFF_FFFF. Perform a write access to a register to clear the counter.

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