3.3.4. Interrupt Request Status register, IRQSTAT

Interrupt Request Status Register. IRQSTAT register status bits cannot be masked. They are set on the corresponding error event regardless of IRQMASK settings.

RW register at offset 0x00C.

Table 3.5. IRQSTAT register

BitsNameDescriptionAccessReset
[31:2]Reserved-RO, RAZ0
1MAN_INV_ERR

Manual invalidation error status. Set when manual invalidation is requested meanwhile the cache is not disabled.

Write 1 to clear.

RW0
0POW_ERR

SRAM power error.

Write 1 to clear.

Power acknowledge de-asserted during operation.

Manual power request de-asserted while cache is enabled and operating in manual power mode.

RW0

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