ARM CoreLink CG092 AHB Flash Cache Technical Reference ManualRevision: r0p0
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3.3.13. Peripheral ID Register, PIDR1

Peripheral ID register.

RO register at offset 0xFE4.

Table 3.14. PIDR1 register

BitsNameDescriptionAccessReset
[31:8]Reserved-RO, RAZ0
[7:4]DES_0PJEP106 identification code bits [3:0].RO0xB
[3:0]PART_1Part number bits [11:8].RO0x8

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