3.3.9. Peripheral ID Register, PIDR5

Peripheral ID register.

RO register at offset 0xFD4.

Table 3.10. PIDR5 register

BitsNameDescriptionAccessReset
[31:8]Reserved-RO, RAZ0
[7:0]Reserved-RO, RAZ0

Copyright © 2016. All rights reserved.ARM DDI 0569A
Non-ConfidentialID040616