3.3.1. Configuration and Control Register, CCR

Configuration and control register.

RW register at offset 0x000.

Table 3.2. CCR register

BitsNameDescriptionAccessReset
[31:7]Reserved-RO, RAZ0
6STATISTIC_EN

Enable statistics logic:

0: Disabled. Counters are stalled.

1: Enable. Counters are running.

RW1
5SET_PREFETCH

Cache Prefetch Setting:

0: Disable prefetch.

1: Enable prefetch.

RW0
4SET_MAN_INV

Cache Invalidate Setting:

0: Automatic cache invalidate when cache enabled.

1: Manual cache invalidate mode.

RW0
3SET_MAN_POW

Power Control Setting:

0: Automatic.

1: Manual.

RW0
2POW_REQManual SRAM power request. RW0
1INV_REQ

Manual invalidate request.

Functional only when SET_MAN_INV is set. Automatically cleared when invalidation is finished or power or invalidation error occurs. Cannot be cleared manually.

Manual invalidation request must be set only when the cache is disabled, otherwise it causes an invalidation error interrupt.

RW0
0EN

Cache Enable:

0: Disable cache.

1: Enable cache.

RW0

Copyright © 2016. All rights reserved.ARM DDI 0569A
Non-ConfidentialID040616