3.3.6. Cache Statistic Hit Register, CSHR

Cache Statistic Hit Register contains the cache hit count.

Including this register in a design is optional. If not present and the register is accessed, a slave OKAY response is given and the register address is RAZ.

RW register at offset 0x014.

Table 3.7. CSHR register

BitsNameDescriptionAccessReset
[31:0]CSHR

Counts the number of cache hits during cache look up.

Only cacheable read transactions are looked up by the CG092.

Writing to the register clears the contents.

RW0

The count value in the registers saturate at 0xFFFF_FFFF. Perform a write access to a register to clear the counter.

Copyright © 2016. All rights reserved.ARM DDI 0569A
Non-ConfidentialID040616