3.3.5. Hardware Parameters register, HWPARAMS

Hardware parameters register holding implementation-defined parameter values.

RO register at offset 0x010.

Table 3.6. HWPARAMS register

BitsNameDescriptionAccessReset
[31:14]Reserved-RO, RAZ0
13GEN_STAT_LOGICIndicates GEN_STAT_LOGIC hardware parameter value.RO1
12RESET_ALL_REGSIndicates RESET_ALL_REGS hardware parameter value.RO1
[11:10]CACHE_WAY

Implementation-defined value for number of cache ways:

  • 1: One cache way.

  • 2: Two cache ways.

RO2
[9:5]CW

Implementation-defined value for cache way width:

  • 8: 256B.

  • 9: 512B.

  • 11: 2KB.

  • 12: 4KB.

RO0x0C
[4:0]AW

Implementation-defined value for AHB-Lite bus width for the flash address space:

  • 18: 256KB.

  • 19: 512KB.

RO0x12

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