A.7. APB slave signals

The table below lists the signals for the APB slave interface to the memory-mapped registers in the CG092.

Table A.10.  APB slave port signals

NameDirectionWidthDescription
PSELInput1Slave select signal.
PENABLEInput1Strobe to time all accesses. Used to indicate the second cycle of an APB transfer.
PADDRInput12 [11:0]Address bus.
PWRITEInput1APB transfer direction.
PWDATAInput3232-bit write data bus.
PRDATAOutput3232-bit read data bus.
PREADYOutput1Driven LOW if extra wait states are required to complete the transfer.
PSLVERROutput1Indicates SLVERR response.
PSTRBInput4

Write strobes. This signal indicates which byte lanes to update during a write transfer. There is one write strobe for each eight bits of the write data bus.

PSTRB[n] corresponds to PWDATA[(8n + 7):(8n)].

Write strobes must not be active during a read transfer

PPROTInput3Protection type.

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