A.4. SRAM signals

The tables below list the SRAM signals for the CG092 subsystem. Way 0 is always present but way 1 is optional and depends on the configuration options selected by the SoC designer.

Table A.4. DATA SRAM signals for way 0

NameDirectionWidthDescription
RAMCLD0ADDROutputImplementation definedParametrized width data address bus.
RAMCLD0WEOutput1Write control for 128 bits (same cycle as address).
RAMCLD0RDOutput4Read control per word (same cycle as address).
RAMCLD0CSOutput4Chip select per word (same cycle as address).
RAMCLD0WDATAOutput128Write data (same cycle as address).
RAMCLD0RDATAInput128Read data (1 cycle after address).

Table A.5. DATA SRAM signals for way 1

NameDirectionWidthDescription
RAMCLD1ADDROutputImplementation definedParametrized width data address bus.
RAMCLD1WEOutput1Write control for 128 bits (same cycle as address).
RAMCLD1RDOutput4Read control per word (same cycle as address).
RAMCLD1CSOutput4Chip select per word (same cycle as address).
RAMCLD1WDATAOutput128Write data (same cycle as address).
RAMCLD1RDATAInput128Read data (1 cycle after address).

The tables below lists the TAG SRAM signals for the eFlash subsystem. Way 0 is always present but way 1 is optional and depends on the configuration options selected by the SoC designer.

Table A.6. TAG SRAM signals for way 0

NameDirectionWidthDescription
RAMTAG0ADDROutputImplementation definedParametrized width data address bus
RAMTAG0WEOutput1Write control (same cycle as address)
RAMTAG0RDOutput1Read control (same cycle as address)
RAMTAG0CSOutput1Chip select (same cycle as address)
RAMTAG0WDATAOutputImplementation definedWrite data (same cycle as address)
RAMTAG0RDATAInputImplementation definedRead data (1 cycle after address)

Table A.7. TAG SRAM signals for way 1

NameDirectionWidthDescription
RAMTAG1ADDROutputImplementation definedParametrized width data address bus
RAMTAG1WEOutput1Write control (same cycle as address)
RAMTAG1RDOutput1Read control (same cycle as address)
RAMTAG1CSOutput1Chip select (same cycle as address)
RAMTAG1WDATAOutputImplementation definedWrite data (same cycle as address)
RAMTAG1RDATAInputImplementation definedRead data (1 cycle after address)

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