A.2. Cache SRAM power control interface

The table below lists the power-control signals for the CG092 subsystem.

Table A.2. Cache SRAM power control interface signals

Signal NameDirectionDescription
RAMPWRUPREQOutput

SRAM power up request. Indicating an SRAM resource request from the cache.

Port is registered and synchronous to HCLK.

RAMPWRUPACKInput

SRAM powers up acknowledge. Indicates that the requested SRAM resource is available.

Port is synchronized to HCLK clock domain.


Copyright © 2016. All rights reserved.ARM DDI 0569A
Non-ConfidentialID040616