2.2.2. Cache SRAM power control

The RAMPWRUPREQ and RAMPWRUPACK signals are implement a full handshake mechanism. To guarantee the safe and correct handshake process the supported cache enable/disable and invalidation scenarios must be used.

Table 2.2. Cache SRAM power control interface signals

Signal NameDirectionDescription
RAMPWRUPREQOutput

SRAM power up request. Indicating an SRAM resource request from the cache.

Port is registered and synchronous to HCLK.

RAMPWRUPACKInput

SRAM powers up acknowledge. Indicates that the requested SRAM resource is available.

Port is synchronized to HCLK clock domain.


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