A.1. Clock and reset signals

The table below lists the clock and reset signals for the CG092 subsystem.

Table A.1. Clock and reset signals

Signal NameDirectionDescription
HCLKInputAHB Bus clock. This clock is used for all always on logic.
PCLKGInputGated clock input for register interface (APB). It must be the same frequency and same phase as HCLK. Can be gated, when there are no APB activities. It is expected to run while APB interface PSEL signal is asserted.
HRESETnInputActive low asynchronous AHB reset. Reset all or a subset of the CG092 registers depending on the RESET_ALL_REGS parameter.

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